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nuc100/120xxxdn aug 31 , 201 5 page 1 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet arm ? cortex ? - m 32 - bit microcontroller numicro ? nuc100 series nuc 1 00 /1 20 xxxdn datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro ? microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvot on.com
nuc100/120xxxdn aug 31 , 201 5 page 2 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet table of c ontents list of f igures ................................ ................................ ................... 6 list of t ables ................................ ................................ .................... 7 1 general desc ription ................................ ............................. 8 2 features ................................ ................................ ............... 9 numicro ? nuc10 0 features C advanced line ................................ .......... 9 2.1 numicro ? nuc120 features C usb line ................................ ............... 13 2.2 3 abbreviations ................................ ................................ ...... 17 4 parts information list and pin configuration ..................... 19 numicro ? nuc100/120xxxdn selection guide ................................ ........ 19 4.1 4.1.1 numicro ? nuc100 advanced line selection guide ................................ ......... 19 4.1.2 numicro ? nuc120 usb line selection guide ................................ ............... 19 pin configuration ................................ ................................ ........... 21 4.2 4.2.1 numicro ? nuc100 pin diagram ................................ ................................ 21 4.2.2 numicro ? nuc120 pin diagram ................................ ................................ 24 pin description ................................ ................................ .............. 27 4.3 4.3.1 numicro ? nuc100 pin description ................................ ............................. 27 4.3.2 numicro ? nuc120 pin description ................................ ............................. 34 5 block diagram ................................ ................................ ...... 4 1 numicro ? nuc100 block diagram ................................ ....................... 41 5.1 numicro ? nuc120 block diagram ................................ ....................... 42 5.2 6 functional description ................................ ........................ 43 arm ? cortex ? - m0 core ................................ ................................ ... 43 6.1 system manager ................................ ................................ ............ 45 6.2 6.2.1 overview ................................ ................................ ........................... 45 6.2.2 system reset ................................ ................................ ..................... 45 6.2.3 powe r modes and wake - up sources ................................ .......................... 51 6.2.4 system power distribution ................................ ................................ ...... 53 6.2.5 system memory map ................................ ................................ ............. 56 6.2.6 system timer (systick) ................................ ................................ ......... 58 6.2.7 nested vectored interrupt controller (nvic) ................................ ................. 59 clock controller ................................ ................................ ............. 60 6.3 6.3.1 overview ................................ ................................ ........................... 60 6.3.2 clock generator ................................ ................................ ................... 62
nuc100/120xxxdn aug 31 , 201 5 page 3 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.3.3 system clock and systick clock ................................ .............................. 63 6.3.4 peripherals clock ................................ ................................ ................. 64 6.3.5 power - down mode clock ................................ ................................ ........ 64 6.3.6 frequency divider output ................................ ................................ ....... 64 flash memory controller (fmc) ................................ .............. 66 6.4 6.4.1 overview ................................ ................................ ........................... 66 6.4.2 features ................................ ................................ ............................ 66 external bus interface (ebi) ................................ .............................. 67 6.5 6.5.1 overview ................................ ................................ ........................... 67 6.5.2 features ................................ ................................ ............................ 67 general purpose i/o (gpio) ................................ .............................. 68 6.6 6.6.1 overview ................................ ................................ ........................... 68 6.6.2 features ................................ ................................ ............................ 68 pdma controller (pdma) ................................ ................................ . 69 6.7 6.7.1 overview ................................ ................................ ........................... 69 6.7.2 features ................................ ................................ ............................ 69 timer controller (tmr) ................................ ................................ .... 70 6.8 6.8.1 overview ................................ ................................ ........................... 70 6.8.2 features ................................ ................................ ............................ 70 pwm generator and capture timer (pwm) ................................ ............ 71 6.9 6.9.1 overview ................................ ................................ ........................... 71 6.9.2 features ................................ ................................ ............................ 72 watchdog timer (wdt) ................................ ................................ ... 73 6.10 6.10.1 overview ................................ ................................ ........................ 73 6.10.2 featu res ................................ ................................ ......................... 73 window watchdog timer (wwdt) ................................ ...................... 74 6.11 6.11.1 overview ................................ ................................ ........................ 74 6.11.2 featu res ................................ ................................ ......................... 74 real time clock (rtc) ................................ ................................ .... 75 6.13 6.13.1 overview ................................ ................................ ........................ 75 6.13.2 features ................................ ................................ ......................... 75 uart interface controller (uart) ................................ ....................... 76 6.14 6.14.1 overview ................................ ................................ ........................ 76 6.14.2 featu res ................................ ................................ ......................... 78 smart card host interface (sc) ................................ .......................... 80 6.15
nuc100/120xxxdn aug 31 , 201 5 page 4 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.15.1 overview ................................ ................................ ........................ 80 6.15.2 features ................................ ................................ ......................... 80 ps/2 device controller (ps2d) ................................ ........................... 81 6.16 6.16.1 overview ................................ ................................ ........................ 81 6.16.2 features ................................ ................................ ......................... 81 i 2 c serial interface controller (i 2 c) ................................ ....................... 82 6.17 6.17.1 overview ................................ ................................ ........................ 82 6.17.2 featu res ................................ ................................ ......................... 83 serial peripheral interface (spi) ................................ .......................... 84 6.18 6.18.1 overview ................................ ................................ ........................ 84 6.18.2 features ................................ ................................ ......................... 84 i 2 s controller (i 2 s) ................................ ................................ .......... 85 6.19 6.19.1 overview ................................ ................................ ........................ 85 6.19.2 featu res ................................ ................................ ......................... 85 usb device controller (usb) ................................ ............................. 86 6.20 6.20.1 overview ................................ ................................ ........................ 86 6.20.2 features ................................ ................................ ......................... 86 analog - to - digital converter (adc) ................................ ....................... 87 6.21 6.21.1 overview ................................ ................................ ........................ 87 6.21.2 features ................................ ................................ ......................... 87 analog comparator (acmp) ................................ .............................. 88 6.22 6.22.1 overview ................................ ................................ ........................ 88 6.22.2 features ................................ ................................ ......................... 88 7 application circuit ................................ ............................... 89 8 electrical characteristics ................................ ................. 90 absolute maximum ratings ................................ ............................... 90 8.1 dc electrical characteristics ................................ .............................. 91 8.2 ac electrical characteristics ................................ .............................. 95 8.3 8.3.1 external 4~24 mhz high speed oscillator ................................ .................... 95 8.3.2 external 4~24 mhz high speed crystal ................................ ....................... 95 8.3.3 external 32.768 khz low speed crystal oscillator ................................ .......... 96 8.3.4 internal 22.1184 mhz high speed oscillator ................................ ................. 96 8.3.5 internal 10 khz low speed oscillator ................................ ......................... 96 analog characteristics ................................ ................................ ..... 97 8.4 8.4.1 12 - bit saradc specification ................................ ................................ ... 97
nuc100/120xxxdn aug 31 , 201 5 page 5 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 8.4.2 ldo and power management specification ................................ .................. 97 8.4.3 low voltage reset specification ................................ ............................... 98 8.4.4 brown - out detector specification ................................ ............................... 98 8.4.5 power - on reset specification ................................ ................................ ... 98 8.4.6 temperature sensor specification ................................ ............................. 99 8.4.7 comparator specification ................................ ................................ ........ 99 8.4.8 usb phy specification ................................ ................................ ......... 100 flash dc electrical characteristics ................................ .................... 102 8.5 9 package dimensions ................................ ........................... 103 100 - pin lqfp (14x14x1.4 mm footprint 2.0 mm) ................................ .... 103 9.1 64 - pin lqfp (10x10x1.4 mm footprint 2.0 mm) ................................ ...... 104 9.2 48 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ......... 105 9.3 10 revision history ................................ ................................ . 106
nuc100/120xxxdn aug 31 , 201 5 page 6 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet list of f igures figure 4 - 1 numicro ? nuc100 series selection code ................................ ................................ ... 20 figure 4 - 2 numicro ? nuc100vxxdn lqfp 100 - pin diagram ................................ ...................... 21 figure 4 - 3 numicro ? nuc100rxxdn lqfp 64 - pin diagram ................................ ........................ 22 figure 4 - 4 numicro ? nuc100lxxdn lqfp 48 - pin diagram ................................ ......................... 23 figure 4 - 5 numicro ? nuc120vxxdn lqfp 100 - pin diagram ................................ ...................... 24 figure 4 - 6 numicro ? nuc120rxxdn lqfp 64 - pin diagram ................................ ........................ 25 figure 4 - 7 numicro ? nuc120lxxdn lqfp 48 - pin diagram ................................ ......................... 26 figure 5 - 1 numicro ? nuc100 block diagram ................................ ................................ ............... 41 figure 5 - 2 numicro ? nuc120 block diagram ................................ ................................ ............... 42 figure 6 - 1 functional controller diagram ................................ ................................ ...................... 43 figure 6 - 2 system reset resources ................................ ................................ ............................. 46 figure 6 - 3 nreset reset waveform ................................ ................................ ............................ 48 figure 6 - 4 power - on reset (por) waveform ................................ ................................ ............... 48 figure 6 - 5 low voltage reset (lvr) waveform ................................ ................................ ............ 49 figure 6 - 6 brown - out detector (bod) waveform ................................ ................................ ......... 50 figure 6 - 7 power mode state machine ................................ ................................ ......................... 51 figure 6 - 8 numicro ? nuc100 power distribution diagram ................................ ........................... 54 figure 6 - 9 numicro ? nuc120 power distribution diagram ................................ ........................... 55 figure 6 - 10 clock generator global view diagram ................................ ................................ ....... 61 figure 6 - 11 clock generator block diagram ................................ ................................ ................. 62 figure 6 - 12 system clock block diagram ................................ ................................ ..................... 63 figure 6 - 13 systick clock control block di agram ................................ ................................ ........ 63 figure 6 - 14 clock source of frequency divider ................................ ................................ ............ 64 figure 6 - 15 frequency divider block diagram ................................ ................................ .............. 65 figure 6 - 16 uart nrts auto - flow control trigger level ................................ ............................ 77 figure 6 - 17 i 2 c bus timing ................................ ................................ ................................ ............ 82 figure 8 - 1 typical crystal application circuit ................................ ................................ ................ 96
nuc100/120xxxdn aug 31 , 201 5 page 7 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet list of t ables table 1 - 1 numicro ? nuc100 series connectivity support table ................................ ................... 8 table 3 - 1 list of abbreviations ................................ ................................ ................................ ....... 18 table 6 - 1 reset value of registers ................................ ................................ ............................... 47 table 6 - 2 power mode difference table ................................ ................................ ....................... 51 table 6 - 3 c lock s in power modes ................................ ................................ ................................ . 52 table 6 - 4 condition of entering power - down mode again ................................ ............................ 53 table 6 - 5 address space assignments for on - chip controllers ................................ ................... 57 table 6 - 6 uart baud rate equation ................................ ................................ ............................ 76 table 6 - 7 uart baud rate setting table ................................ ................................ ..................... 77
nuc100/120xxxdn aug 31 , 201 5 page 8 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 1 general description the numicro ? nuc100 series 32 - bit microcontroller (mcu) is embedded with the arm ? cortex ? - m0 core with the cost equivalent to traditional 8 - bit mcu. the nuc100 s eries can be used in consumer electronics, industrial control and applications which requiring rich communi cation interfaces such as industrial automation, alarm system, energy system and power system. the numicro ? nuc1 00 advanced line and nuc120 usb line are embed ded with the cortex ? - m0 core running up to 50 mhz and features 32/64/128 kbyte s f lash , 4/8/16 kbyte s embedded sram and 4 kbyte s loader rom for the isp. it operates at a wide voltage range of 2.5v ~ 5.5v and temperature range of - 40 ~ +85 . the nuc100 s eries is also provided with plenty of peripheral devices, such as timers, watchdog timer, window watchdog timer, rtc, pdma with crc calculation uni t , uart, spi, i 2 c, i 2 s, pwm timer, gpio, ps / 2, ebi, smart card host, 12 - bit adc, analog comparator, low voltage reset controller and brown - out detector. additionally, the nuc120 usb line is equip ped with a usb 2.0 full - speed device. t hese peripherals have been incorporated into the nuc1 00 series to reduce component count, board space and system cost. t he nuc1 00 series is equipped with isp (in - system programming) , iap ( in - application - programming ) and icp (in - circuit programming) functions, which allow s the user to update the program under software control through the on - chip connectivity interface, such as swd, uart and usb . product line uart spi i 2 c usb ps / 2 i 2 s sc nuc100 xxxdn 3 4 2 - 1 1 3 nuc120 xxxdn 3 4 2 1 1 1 3 table 1 - 1 numicro ? nuc1 00 series connectivity support table
nuc100/120xxxdn aug 31 , 201 5 page 9 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 2 features the equipped features are dependent on the product line and their sub product s. numicro ? nuc1 00 features C advanced line 2.1 ? arm ? cortex ? - m0 core C r uns up to 50 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? bu il t - in ldo for wide operating voltage range d from 2.5 v to 5.5 v ? flash memory C 32/64/128 kbytes flash for program code C 4 kb flash for isp loader C support s in - s ystem - p rogram (isp) and in - application - program (iap) application code update C 512 byte page erase for flash C configurable data flash address and size for 128 kb system, fixed 4 kb data flash for the 32 kb and 64 kb system C support s 2 - wire d icp update through swd/ice interface C support s fast parallel programming mode by external programmer ? sram memory C 4/8/16 kbytes embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 9 channels pdma for automatic data transfer between sram and peripherals C support s crc calculation with four common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C built - in 22.1184 mhz high speed oscillator for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at - 40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built - in 10 k hz low speed oscillator for watchdog timer and wake - up operation C support s one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - d rain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting ? timer
nuc100/120xxxdn aug 31 , 201 5 page 10 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes C support s event counting function C support s input capture function ? watchdog timer C multiple clock sources C 8 selectable time - out period from 1. 6 ms ~ 26 .0 sec (depend ing on clock source) C wake - up from p ower - down or i dle mode C interrupt or reset selectable on watchdog time - out ? window watchdog timer C 6 - bit down counter with 11 - bit prescale for wide range window selected ? rtc C support s software compensation by setting frequency compensate register (fcr) C support s rtc counter (second, minute, hour) and calendar counter (day, month, year) C support s alarm registers (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C automatic leap year recognition C support s periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support s wake - up fu nction ? pwm /capture C u p to four built - in 16 - bit pwm generators provid ing eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for complementary paired pwm C up to eight 16 - bit digital c apture timers (shared with pwm timers) provid ing eight rising/falling capture inputs C support s capture interrupt ? uart C up to three uart controllers C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 6 4 - byte fifo is for high speed C uart1/2(optional) with 1 6 - byte fifo for standard device C support s irda (sir) and lin function C support s rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock C support s pdma mode ? spi C up to four sets of spi controller s C spi clock rate of master can be up to 36 mhz (chip working at 5v) ; spi clock rate of slave can be up to 18 mhz (chip working at 5v) C support s spi m aster/ s lave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C two slave/device select lines in m aster mode , and one slave/device select line in slave mode C s upport s b yte s uspend mode in 32 - bit transmission C support s pdma mode
nuc100/120xxxdn aug 31 , 201 5 page 11 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C support s three wire, no slave select signal, bi - direction interfac e ? i 2 c C up to two sets of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C ser ial clock synchronization allow ing devices with different bit rates to communicate via one serial bus C serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow ing for versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up function ? i 2 s C interface with external audio codec C operate as either m aster or s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and stereo audio data C supports i 2 s and msb justified data format C provides t wo 8 word fifo data buffers, one for transmit ting and the other for receiv ing C generates interrupt requests when buffer levels cross a programmable boundary C support s two dma requests, one for transmit ting and the other for receiv ing ? ps/2 device C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s oftware override bus ? ebi (external bus interface) C accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode C support s 8 - /16 - bit data width C support s byte write in 16 - bit data width mode ? adc C 12 - bit sar adc with 7 6 0 k sps C up to 8 - ch single - end input or 4 - ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start ed by software programming or external input C support s pdma mode ? analog comparator C up to two analog comparator s C external input or internal b and - gap voltage selectable at negative node C interrupt when compare result s change C supports p ower - down wake - up ? smart card host (sc) C compliant to iso - 7816 - 3 t=0, t=1 C support s up to t hree iso - 7816 - 3 ports
nuc100/120xxxdn aug 31 , 201 5 page 12 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C separate receive / transmit 4 bytes entry fifo for data payloads C programmable transmission clock frequency C programmable receiver buffer trigger level C programmable guard time selection (11 etu ~ 266 etu) C one 24 - bit and two 8 - bit time - out counter s for answer to request (atr) and waiting times processing C support s auto inverse convention function C support s transmitt er and receiver error retry and error limit function C support s hardware activation sequence process C support s hardware warm reset sequence process C support s hardware deactivation sequence process C support s hardware auto deactivation sequence when detect ing the card is removal ? 96 - bit unique id (uid) ? o ne built - in t emperature sensor with 1 resolution ? brown - out d etector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage level : 2.0 v ? operating temperature: - 40 ~ 85 ? packages: C all green package (rohs) C lqfp 100 - pin C lqfp 64 - pin C lqfp 48 - pin
nuc100/120xxxdn aug 31 , 201 5 page 13 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet numicro ? nuc1 20 features C usb line 2.2 ? arm ? cortex ? - m0 core C r uns up to 50 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? buil t - in ldo for wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32/64/128 kbytes flash for program code C 4 kb flash for isp loader C support s in - s ystem - p rogram (isp) and in - application - program (iap) application code update C 512 byte page erase for flash C configurable data flash address and size for 128 kb system, fixed 4 kb data flash for the 32 kb and 64 kb system C support s 2 - wire d icp update through swd/ice interface C support s fast parallel programming mode by external programmer ? sram memory C 4/8/16 kbytes embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 9 channels pdma for automatic data transfer between sram and peripherals C support s crc calculation with four common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C built - in 22.1184 mhz high speed oscillator for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at - 40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built - in 10 k hz low speed oscillator for watchdog timer and wake - up operation C support s one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for usb and precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - d rain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting ? timer C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes
nuc100/120xxxdn aug 31 , 201 5 page 14 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C support s event counting function C support s input capture function ? watchdog timer C multiple clock sources C 8 selectable time - out period from 1. 6 ms ~ 26 .0 sec (depend ing on clock source) C w ake - up from p ower - down or i dle mode C interrupt or reset selectable on watchdog time - out ? window watchdog timer C 6 - bit down counter with 11 - bit prescale for wide range window selected ? rtc C support s software compensation by setting frequency compensate register (fcr) C support s rtc counter (second, minute, hour) and calendar counter (day, month, year) C support s alarm regis ters (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C automatic leap year recognition C support s periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support s wake - up function ? pwm /capture C u p to four built - in 16 - bit pwm generators provid ing eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for compl ementary paired pwm C up to eight 16 - bit digital c apture timers (shared with pwm timers) provid ing eight rising/falling capture inputs C support s c apture interrupt ? uart C up to three uart controllers C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 6 4 - byte fifo is for high speed C uart1/2(optional) with 1 6 - byte fifo for standard device C support s irda (sir) and lin function C support s rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock C support s pdma mode ? spi C up to four sets of spi controller s C the maximum spi clock rate of master can up to 36 mhz (chip working at 5v) C the maximum spi clock rate of slave can up to 18 mhz (chip working at 5v) C support s spi m aster/ s lave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C two slave/device select lines in m aster mode , and one slave/device select line in slave mode C support s b yte s uspend mode in 32 - bit transmission C support s pdma mode C support s three wire, no slave select signal, bi - direction interfac e ? i 2 c
nuc100/120xxxdn aug 31 , 201 5 page 15 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C up to two sets of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C ser ial clock synchronization allow ing devices with different bit rates to communicate via one serial bus C serial clock synchronizat ion used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow ing for versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up function ? i 2 s C interface with external audio codec C operate as either m aster or s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and s tereo audio data C supports i 2 s and msb justified data format C provides t wo 8 word fifo data buffers, one for transmit ting and the other for receiv ing C generates interrupt requests when buffer levels cross a programmable boundary C support s two dma requests, one for transmit ting and the other for receiv ing ? ps/2 device C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C software override bus ? ebi (external bus interface) C accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode C support s 8 - /16 - bit data width C support s byte write in 16 - bit data width mode ? usb 2.0 full - speed device C one set of usb 2.0 fs device 12 mbps C on - chip usb transceiver C provide s 1 interrupt source with 4 interrupt events C support s control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide s 6 programmable endpoints C include s 512 bytes internal sram as usb buffer C provide s remote wake - up capability ? adc C 12 - bit sar adc with 7 6 0 k sps C up to 8 - ch single - end input or 4 - ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start ed by software programming or exter nal input C support s pdma m ode ? analog comparator
nuc100/120xxxdn aug 31 , 201 5 page 16 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C up to two analog comparator s C external input or internal b and - gap voltage selectable at negative node C interrupt when compare result s change C support s p ower - down wake - up ? smart card host (sc) C compliant to iso - 7816 - 3 t=0, t=1 C support s up to t hree iso - 7816 - 3 ports C separate receive / transmit 4 bytes entry fifo for data payloads C programmable transmission clock frequency C programmable receiver buffer trigger level C programmable guard time selection (11 etu ~ 266 etu) C one 24 - bit and two 8 - bit time - out counter s for answer to request (atr) and waiting times processing C support s auto inverse convention function C support s transmitter and receiver error retry and error limit function C support s hardware activation sequence process C support s hardware warm reset sequence process C support s hardware deactivation sequence process C support s hardware auto deactivation sequence when detect ing the card removal ? 96 - bit unique id (uid) ? one built - in t emperature sensor with 1 resolution ? brown - out d etector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage level: 2.0 v ? operating temperature: - 40 ~ 85 ? packages: C all green package (rohs) C lqfp 100 - pin C lqfp 64 - pin C lqfp 48 - pin
nuc100/120xxxdn aug 31 , 201 5 page 17 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection can controller area network dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sdio secure digital input/output spi serial peripheral interface
nuc100/120xxxdn aug 31 , 201 5 page 18 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet sps samples per second tdes triple data encryption standard tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3 - 1 list of abbreviations
nuc100/120xxxdn aug 31 , 201 5 page 19 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 4 parts information li st and pin configuration numicro ? nuc 1 00/ 1 20xxx d n selection guide 4.1 4.1.1 numicro ? nuc1 00 advance d line selection guide part n umber aprom ram data flash isp loader rom i / o timer connectivity i 2 s sc co mp . pwm adc rtc ebi isp icp package uart spi i 2 c usb lin can nuc100lc1 d n 32 kb 4 kb 4 kb 4 kb up to 37 4x32 - bit 2 1 2 - - - 1 3 1 6 8 x12 - bit v - v lqfp48 nuc100ld1 d n 64 kb 4 kb 4 kb 4 kb up to 37 4x32 - bit 2 1 2 - - - 1 3 1 6 8 x12 - bit v - v lqfp48 nuc100ld2 d n 64 kb 8 kb 4 kb 4 kb up to 37 4x32 - bit 2 1 2 - - - 1 3 1 6 8 x12 - bit v - v lqfp48 nuc100ld3 d n 64 kb 16 kb 4 kb 4 kb up to 37 4x32 - bit 2 1 2 - - - 1 3 1 6 8 x12 - bit v - v lqfp48 nuc100le3 d n 128 kb 16 kb defin able 4 kb up to 37 4x32 - bit 2 1 2 - - - 1 3 1 6 8 x12 - bit v - v lqfp48 nuc100rc1 d n 32 kb 4 kb 4 kb 4 kb up to 51 4x32 - bit 3 2 2 - - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc100rd1 d n 64 kb 4 kb 4 kb 4 kb up to 51 4x32 - bit 3 2 2 - - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc100rd2 d n 64 kb 8 kb 4 kb 4 kb up to 51 4x32 - bit 3 2 2 - - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc100rd3 d n 64 kb 16 kb 4 kb 4 kb up to 51 4x32 - bit 3 2 2 - - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc100re3 d n 128 kb 16 kb defin able 4 kb up to 51 4x32 - bit 3 2 2 - - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc100vd2 d n 64 kb 8 kb 4 kb 4 kb up to 8 4 4x32 - bit 3 4 2 - - - 1 3 2 8 8x12 - bit v v v lqfp100 nuc100vd3 d n 64 kb 16 kb 4 kb 4 kb up to 8 4 4x32 - bit 3 4 2 - - - 1 3 2 8 8x12 - bit v v v lqfp100 nuc100ve3 d n 128 kb 16 kb defin able 4 kb up to 8 4 4x32 - bit 3 4 2 - - - 1 3 2 8 8x12 - bit v v v lqfp100 4.1.2 numicro ? nuc1 20 usb line selection guide part number aprom ram data flash isp loader rom i / o timer connectivity i 2 s sc co mp. pwm adc rtc ebi isp icp package uart spi i 2 c usb lin can nuc1 2 0lc1 d n 32 kb 4 kb 4 kb 4 kb up to 33 4x32 - bit 2 1 2 1 - - 1 3 1 4 8 x12 - bit v - v lqfp48 nuc1 2 0ld1 d n 64 kb 4 kb 4 kb 4 kb up to 33 4x32 - bit 2 1 2 1 - - 1 3 1 4 8 x12 - bit v - v lqfp48 nuc1 2 0ld2 d n 64 kb 8 kb 4 kb 4 kb up to 33 4x32 - bit 2 1 2 1 - - 1 3 1 4 8 x12 - bit v - v lqfp48 nuc1 2 0ld3 d n 64 kb 16 kb 4 kb 4 kb up to 33 4x32 - bit 2 1 2 1 - - 1 3 1 4 8 x12 - bit v - v lqfp48 nuc1 2 0le3 d n 128 kb 16 kb defin able 4 kb up to 33 4x32 - bit 2 1 2 1 - - 1 3 1 4 8 x12 - bit v - v lqfp48
nuc100/120xxxdn aug 31 , 201 5 page 20 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet nuc1 2 0rc1 d n 32 kb 4 kb 4 kb 4 kb up to 47 4x32 - bit 2 2 2 1 - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc1 2 0rd1 d n 64 kb 4 kb 4 kb 4 kb up to 47 4x32 - bit 2 2 2 1 - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc1 2 0rd2 d n 64 kb 8 kb 4 kb 4 kb up to 47 4x32 - bit 2 2 2 1 - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc1 2 0rd3 d n 64 kb 16 kb 4 kb 4 kb up to 47 4x32 - bit 2 2 2 1 - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc1 2 0re3 d n 128 kb 16 kb defin able 4 kb up to 47 4x32 - bit 2 2 2 1 - - 1 3 2 6 8 x12 - bit v v v lqfp64 nuc1 2 0vd2 d n 64 kb 8 kb 4 kb 4 kb up to 8 0 4x32 - bit 3 4 2 1 - - 1 3 2 8 8x12 - bit v v v lqfp100 nuc1 2 0vd3 d n 64 kb 16 kb 4 kb 4 kb up to 8 0 4x32 - bit 3 4 2 1 - - 1 3 2 8 8x12 - bit v v v lqfp100 nuc1 2 0ve3 d n 128 kb 16 kb defin able 4 kb up to 8 0 4x32 - bit 3 4 2 1 - - 1 3 2 8 8x12 - bit v v v lqfp100 figure 4 - 1 numicro ? nuc 1 00 series s election c ode n u c 1 0 - x x a r m - b a s e d 3 2 - b i t m i c r o c o n t r o l l e r 0 : a d v a n c e d l i n e 2 : u s b l i n e 3 : a u t o m o t i v e l i n e 4 : c o n n e c t i v i t y l i n e c p u c o r e 1 / 2 : c o r t e x - m 0 5 / 7 : a r m 7 9 : a r m 9 t e m p e r a t u r e n : - 4 0 r e s e r v e x x f u n c t i o n 0 p a c k a g e t y p e y : q f n 3 6 l : l q f p 4 8 r : l q f p 6 4 v : l q f p 1 0 0 x r a m s i z e 1 : 4 k b 2 : 8 k b 3 : 1 6 k b a p r o m s i z e a : 8 k b b : 1 6 k b c : 3 2 k b d : 6 4 k b e : 1 2 8 k b
nuc100/120xxxdn aug 31 , 201 5 page 21 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin configuration 4.2 4.2.1 numicro ? nuc 1 00 pin diagram numicro ? nuc 1 0 0 vxx d n lqfp 100 pin 4.2.1.1 figure 4 - 2 numicro ? nuc 1 00vxx d n lqfp 100 - pin diagram s c 1 r s t / a d 8 / a d c 5 / p a . 5 s c 1 c l k / a d 7 / a d c 6 / p a . 6 s c 1 d a t / a d 6 / a d c 7 / s p i s s 2 1 / p a . 7 s p i s s 3 1 / i n t 0 / p b . 1 4 a d 1 / c p o 1 / p b . 1 3 a d 0 / c l k o / c p o 0 / p b . 1 2 x 3 2 i x 3 2 o n r d / i 2 c 1 s c l / p a . 1 1 n w r / i 2 c 1 s d a / p a . 1 0 i 2 c 0 s c l / p a . 9 i 2 c 0 s d a / p a . 8 r x d 1 / p b . 4 t x d 1 / p b . 5 a l e / r t s 1 / p b . 6 n c s / c t s 1 / p b . 7 l d o v d d v s s s c 1 c d / a d 5 / c p n 0 / p c . 7 s c 0 c d / a d 4 / c p p 0 / p c . 6 a d 3 / c p n 1 / p c . 1 5 a d 2 / c p p 1 / p c . 1 4 t 0 e x / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 / r e s e t t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / a d 9 / s c 1 p w r p a . 3 / a d c 3 / a d 1 0 / s c 0 d a t p a . 2 / a d c 2 / a d 1 1 / s c 0 c l k p a . 1 / a d c 1 / a d 1 2 / s c 0 r s t p a . 0 / a d c 0 / s c 0 p w r a v s s i c e _ c k i c e _ d a t p a . 1 2 / p w m 0 / a d 1 3 / s c 2 d a t p a . 1 3 / p w m 1 / a d 1 4 / s c 2 c l k p a . 1 4 / p w m 2 / a d 1 5 / s c 2 r s t p a . 1 5 / p w m 3 / i 2 s m c l k / s c 2 p w r p c . 8 / s p i s s 1 0 / m c l k p c . 9 / s p i c l k 1 a v d d v s s v d d p v s s p c . 0 / s p i s s 0 0 / i 2 s l r c l k p c . 1 / s p i c l k 0 / i 2 s b c l k p c . 2 / m i s o 0 0 / i 2 s d i p c . 3 / m o s i 0 0 / i 2 s d o p d . 1 5 / t x d 2 p d . 1 4 / r x d 2 p d . 7 p d . 6 p b . 3 / c t s 0 / t 3 e x / n w r h / s c 2 c d p b . 2 / r t s 0 / t 2 e x / n w r l p b . 1 / t x d 0 p b . 0 / r x d 0 p e . 7 p e . 8 p e . 9 p e . 1 0 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 / m i s o 1 0 p c . 1 1 / m o s i 1 0 n u c 1 0 0 v x x d n l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 s p i s s 3 0 / p d . 8 s p i c l k 3 / p d . 9 m i s o 3 0 / p d . 1 0 m o s i 3 0 / p d . 1 1 m i s o 3 1 / p d . 1 2 m o s i 3 1 / p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 1 1 p e . 1 2 p c . 4 / m i s o 0 1 p c . 5 / m o s i 0 1 p b . 9 / t m 0 / s p i s s 1 1 p b . 1 0 / t m 1 / s p i s s 0 1 p b . 1 1 / t m 2 / p w m 4 p e . 5 / t 1 e x / p w m 5 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 / m i s o 1 1 p c . 1 3 / m o s i 1 1 p e . 0 / p w m 6 p e . 1 / p w m 7 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p s 2 d a t / p f . 2 p s 2 c l k / p f . 3 s p i s s 2 0 / p d . 0 s p i c l k 2 / p d . 1 m i s o 2 0 / p d . 2 m o s i 2 0 / p d . 3 m i s o 2 1 / p d . 4 m o s i 2 1 / p d . 5 v r e f
nuc100/120xxxdn aug 31 , 201 5 page 22 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet numicro ? nuc 1 0 0 rxx d n lqfp 64 pin 4.2.1.2 figure 4 - 3 numicro ? nuc 1 00rxx d n lqfp 64 - pin diagram s c 1 r s t / a d 8 / a d c 5 / p a . 5 s c 1 c l k / a d 7 / a d c 6 / p a . 6 s c 1 d a t / a d 6 / a d c 7 / p a . 7 i n t 0 / p b . 1 4 a d 1 / c p o 1 / p b . 1 3 a d 0 / c l k o / c p o 0 / p b . 1 2 x 3 2 i x 3 2 o n r d / i 2 c 1 s c l / p a . 1 1 n w r / i 2 c 1 s d a / p a . 1 0 i 2 c 0 s c l / p a . 9 i 2 c 0 s d a / p a . 8 r x d 1 / p b . 4 t x d 1 / p b . 5 a l e / r t s 1 / p b . 6 n c s / c t s 1 / p b . 7 l d o v d d v s s s c 1 c d / a d 5 / c p n 0 / p c . 7 s c 0 c d / a d 4 / c p p 0 / p c . 6 a d 3 / c p n 1 / p c . 1 5 a d 2 / c p p 1 / p c . 1 4 t 0 e x / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 / r e s e t t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / a d 9 / s c 1 p w r p a . 3 / a d c 3 / a d 1 0 / s c 0 d a t p a . 2 / a d c 2 / a d 1 1 / s c 0 c l k p a . 1 / a d c 1 / a d 1 2 / s c 0 r s t p a . 0 / a d c 0 / s c 0 p w r a v s s i c e _ c k i c e _ d a t p a . 1 2 / p w m 0 / a d 1 3 / s c 2 d a t p a . 1 3 / p w m 1 / a d 1 4 / s c 2 c l k p a . 1 4 / p w m 2 / a d 1 5 / s c 2 r s t p a . 1 5 / p w m 3 / i 2 s m c l k / s c 2 p w r p c . 8 / s p i s s 1 0 / m c l k p c . 9 / s p i c l k 1 a v d d v s s v d d p v s s p c . 0 / s p i s s 0 0 / i 2 s l r c l k p c . 1 / s p i c l k 0 / i 2 s b c l k p c . 2 / m i s o 0 0 / i 2 s d i p c . 3 / m o s i 0 0 / i 2 s d o 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / m i s o 1 0 p c . 1 1 / m o s i 1 0 p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t 1 e x / p w m 5 p d . 1 5 / t x d 2 p d . 1 4 / r x d 2 p d . 7 p d . 6 p b . 3 / c t s 0 / t 3 e x / n w r h / s c 2 c d p b . 2 / r t s 0 / t 2 e x / n w r l p b . 1 / t x d 0 p b . 0 / r x d 0 n u c 1 0 0 r x x d n l q f p 6 4 - p i n
nuc100/120xxxdn aug 31 , 201 5 page 23 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet numicro ? nuc 1 0 0 lxx d n lqfp 48 pin 4.2.1.3 figure 4 - 4 numicro ? nuc 1 00lxx d n lqfp 48 - pin diagram s c 1 r s t / a d c 5 / p a . 5 s c 1 c l k / a d c 6 / p a . 6 s c 1 d a t / a d c 7 / p a . 7 c l k o / c p o 0 / p b . 1 2 x 3 2 i x 3 2 o i 2 c 1 s c l / p a . 1 1 i 2 c 1 s d a / p a . 1 0 i 2 c 0 s c l / p a . 9 i 2 c 0 s d a / p a . 8 r x d 1 / p b . 4 t x d 1 / p b . 5 l d o v d d v s s s c 1 c d / c p n 0 / p c . 7 s c 0 c d / c p p 0 / p c . 6 t 0 e x / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 / r e s e t t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / s c 1 p w r p a . 3 / a d c 3 / s c 0 d a t p a . 2 / a d c 2 / s c 0 c l k p a . 1 / a d c 1 / s c 0 r s t p a . 0 / a d c 0 / s c 0 p w r a v s s i c e _ c k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 d a t p a . 1 3 / p w m 1 / s c 2 c l k p a . 1 4 / p w m 2 / s c 2 r s t p a . 1 5 / p w m 3 / i 2 s m c l k / s c 2 p w r a v d d p v s s p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t 1 e x / p w m 5 p b . 3 / c t s 0 / t 3 e x / s c 2 c d p b . 2 / r t s 0 / t 2 e x 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 1 0 0 l x x d n l q f p 4 8 - p i n p b . 1 / t x d 0 p b . 0 / r x d 0 p c . 0 / s p i s s 0 0 / i 2 s l r c l k p c . 1 / s p i c l k 0 / i 2 s b c l k p c . 2 / m i s o 0 0 / i 2 s d i p c . 3 / m o s i 0 0 / i 2 s d o
nuc100/120xxxdn aug 31 , 201 5 page 24 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 4.2.2 numicro ? nuc 1 20 pin diagram numicro ? nuc 1 20 vxx d n lqfp 100 pin 4.2.2.1 figure 4 - 5 numicro ? nuc 1 20vxx d n lqfp 100 - pin diagram s c 1 r s t / a d 8 / a d c 5 / p a . 5 s c 1 c l k / a d 7 / a d c 6 / p a . 6 s c 1 d a t / a d 6 / a d c 7 / s p i s s 2 1 / p a . 7 s p i s s 3 1 / i n t 0 / p b . 1 4 a d 1 / c p o 1 / p b . 1 3 a d 0 / c l k o / c p o 0 / p b . 1 2 x 3 2 i x 3 2 o n r d / i 2 c 1 s c l / p a . 1 1 n w r / i 2 c 1 s d a / p a . 1 0 i 2 c 0 s c l / p a . 9 i 2 c 0 s d a / p a . 8 r x d 1 / p b . 4 t x d 1 / p b . 5 a l e / r t s 1 / p b . 6 n c s / c t s 1 / p b . 7 l d o v d d v s s s c 1 c d / a d 5 / c p n 0 / p c . 7 s c 0 c d / a d 4 / c p p 0 / p c . 6 a d 3 / c p n 1 / p c . 1 5 a d 2 / c p p 1 / p c . 1 4 t 0 e x / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 / r e s e t t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / a d 9 / s c 1 p w r p a . 3 / a d c 3 / a d 1 0 / s c 0 d a t p a . 2 / a d c 2 / a d 1 1 / s c 0 c l k p a . 1 / a d c 1 / a d 1 2 / s c 0 r s t p a . 0 / a d c 0 / s c 0 p w r a v s s i c e _ c k i c e _ d a t p a . 1 2 / p w m 0 / a d 1 3 / s c 2 d a t p a . 1 3 / p w m 1 / a d 1 4 / s c 2 c l k p a . 1 4 / p w m 2 / a d 1 5 / s c 2 r s t p a . 1 5 / p w m 3 / i 2 s m c l k / s c 2 p w r p c . 8 / s p i s s 1 0 / m c l k p c . 9 / s p i c l k 1 a v d d v s s v d d p v s s p c . 0 / s p i s s 0 0 / i 2 s l r c l k p c . 1 / s p i c l k 0 / i 2 s b c l k p c . 2 / m i s o 0 0 / i 2 s d i p c . 3 / m o s i 0 0 / i 2 s d o p d . 1 5 / t x d 2 p d . 1 4 / r x d 2 p d . 7 p d . 6 p b . 3 / c t s 0 / t 3 e x / n w r h / s c 2 c d p b . 2 / r t s 0 / t 2 e x / n w r l p b . 1 / t x d 0 p b . 0 / r x d 0 d + d - v d d 3 3 v b u s 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 / m i s o 1 0 p c . 1 1 / m o s i 1 0 n u c 1 2 0 v x x d n l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 s p i s s 3 0 / p d . 8 s p i c l k 3 / p d . 9 m i s o 3 0 / p d . 1 0 m o s i 3 0 / p d . 1 1 m i s o 3 1 / p d . 1 2 m o s i 3 1 / p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 7 p e . 8 p c . 4 / m i s o 0 1 p c . 5 / m o s i 0 1 p b . 9 / t m 1 / s p i s s 1 1 p b . 1 0 / t m 2 / s p i s s 0 1 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t 1 e x / p w m 5 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 / m i s o 1 1 p c . 1 3 / m o s i 1 1 p e . 0 / p w m 6 p e . 1 / p w m 7 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p s 2 d a t / p f . 2 p s 2 c l k / p f . 3 s p i s s 2 0 / p d . 0 s p i c l k 2 / p d . 1 m i s o 2 0 / p d . 2 m o s i 2 0 / p d . 3 m i s o 2 1 / p d . 4 m o s i 2 1 / p d . 5 v r e f
nuc100/120xxxdn aug 31 , 201 5 page 25 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet numicro ? nuc 1 20 rxx d n lqfp 64 pin 4.2.2.2 figure 4 - 6 numicro ? nuc 1 20rxx d n lqfp 64 - pin diagram s c 1 r s t / a d 8 / a d c 5 / p a . 5 s c 1 c l k / a d 7 / a d c 6 / p a . 6 s c 1 d a t / a d 6 / a d c 7 / p a . 7 i n t 0 / p b . 1 4 a d 1 / c p o 1 / p b . 1 3 a d 0 / c l k o / c p o 0 / p b . 1 2 x 3 2 i x 3 2 o n r d / i 2 c 1 s c l / p a . 1 1 n w r / i 2 c 1 s d a / p a . 1 0 i 2 c 0 s c l / p a . 9 i 2 c 0 s d a / p a . 8 r x d 1 / p b . 4 t x d 1 / p b . 5 a l e / r t s 1 / p b . 6 n c s / c t s 1 / p b . 7 l d o v d d v s s s c 1 c d / a d 5 / c p n 0 / p c . 7 s c 0 c d / a d 4 / c p p 0 / p c . 6 a d 3 / c p n 1 / p c . 1 5 a d 2 / c p p 1 / p c . 1 4 t 0 e x / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 / r e s e t t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / a d 9 / s c 1 p w r p a . 3 / a d c 3 / a d 1 0 / s c 0 d a t p a . 2 / a d c 2 / a d 1 1 / s c 0 c l k p a . 1 / a d c 1 / a d 1 2 / s c 0 r s t p a . 0 / a d c 0 / s c 0 p w r a v s s i c e _ c k i c e _ d a t p a . 1 2 / p w m 0 / a d 1 3 / s c 2 d a t p a . 1 3 / p w m 1 / a d 1 4 / s c 2 c l k p a . 1 4 / p w m 2 / a d 1 5 / s c 2 r s t p a . 1 5 / p w m 3 / i 2 s m c l k / s c 2 p w r p c . 8 / s p i s s 1 0 / m c l k p c . 9 / s p i c l k 1 a v d d v s s v d d p v s s p c . 0 / s p i s s 0 0 / i 2 s l r c l k p c . 1 / s p i c l k 0 / i 2 s b c l k p c . 2 / m i s o 0 0 / i 2 s d i p c . 3 / m o s i 0 0 / i 2 s d o d + d - v d d 3 3 v b u s 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / m i s o 1 0 p c . 1 1 / m o s i 1 0 p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t 1 e x / p w m 5 p b . 3 / c t s 0 / t 3 e x / n w r h / s c 2 c d p b . 2 / r t s 0 / t 2 e x / n w r l p b . 1 / t x d 0 p b . 0 / r x d 0 n u c 1 2 0 r x x d n l q f p 6 4 - p i n
nuc100/120xxxdn aug 31 , 201 5 page 26 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet numicro ? nuc 1 20 lxx d n lqfp 48 pin 4.2.2.3 figure 4 - 7 numicro ? nuc 1 20lxx d n lqfp 48 - pin diagram s c 1 r s t / a d c 5 / p a . 5 s c 1 c l k / a d c 6 / p a . 6 s c 1 d a t / a d c 7 / p a . 7 c l k o / c p o 0 / p b . 1 2 x 3 2 i x 3 2 o i 2 c 1 s c l / p a . 1 1 i 2 c 1 s d a / p a . 1 0 i 2 c 0 s c l / p a . 9 i 2 c 0 s d a / p a . 8 r x d 1 / p b . 4 t x d 1 / p b . 5 l d o v d d v s s s c 1 c d / c p n 0 / p c . 7 s c 0 c d / c p p 0 / p c . 6 t 0 e x / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 / r e s e t t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / s c 1 p w r p a . 3 / a d c 3 / s c 0 d a t p a . 2 / a d c 2 / s c 0 c l k p a . 1 / a d c 1 / s c 0 r s t p a . 0 / a d c 0 / s c 0 p w r a v s s i c e _ c k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 d a t p a . 1 3 / p w m 1 / s c 2 c l k p a . 1 4 / p w m 2 / s c 2 r s t p a . 1 5 / p w m 3 / i 2 s m c l k / s c 2 p w r a v d d p v s s p c . 0 / s p i s s 0 0 / i 2 s l r c l k p c . 1 / s p i c l k 0 / i 2 s b c l k p c . 2 / m i s o 0 0 / i 2 s d i p c . 3 / m o s i 0 0 / i 2 s d o p b . 3 / c t s 0 / t 3 e x / s c 2 c d p b . 2 / r t s 0 / t 2 e x p b . 1 / t x d 0 p b . 0 / r x d 0 d + d - v d d 3 3 v b u s 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 1 2 0 l x x d n l q f p 4 8 - p i n
nuc100/120xxxdn aug 31 , 201 5 page 27 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin description 4.3 4.3.1 numicro ? nuc 1 00 pin description pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.15 i/o general purpose digital i/o pin. 2 pe.14 i/o general purpose digital i/o pin. 3 pe.13 i/o general purpose digital i/o pin. 4 1 pb.14 i/o general purpose digital i/o pin. / int0 i external interrupt 0 input pin . spiss 3 1 i/o 2 nd spi3 slave select pin . 5 2 pb.13 i/o general purpose digital i/o pin. cpo1 o comparator1 output pin . ad1 i/o ebi address/data bus bit1 6 3 1 pb.12 i/o general purpose digital i/o pin. cpo0 o comparator0 output pin clko o frequency divider output pin ad0 i/o ebi address/data bus bit0 7 4 2 x32o o external 32.768 khz low speed crystal output pin 8 5 3 x32i i external 32.768 khz low speed crystal input pin 9 6 4 pa.11 i/o general purpose digital i/o pin. i2c1scl i/o i 2 c 1 clock pin . nrd o ebi read enable output pin 10 7 5 pa.10 i/o general purpose digital i/o pin. i2c1sda i/o i 2 c 1 data input/output pin . nwr o ebi write enable output pin 11 8 6 pa.9 i/o general purpose digital i/o pin. i2c0scl i/o i 2 c0 clock pin . 12 9 7 pa.8 i/o general purpose digital i/o pin. i2c0sda i/o i 2 c0 data input/output pin . 13 pd.8 i/o general purpose digital i/o pin. spiss 30 i/o 1 st spi3 slave select pin . 14 pd.9 i/o general purpose digital i/o pin. sp i clk3 i/o spi3 serial clock pin . 15 pd.10 i/o general purpose digital i/o pin.
nuc100/120xxxdn aug 31 , 201 5 page 28 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin miso 30 i/o 1 st spi3 miso (master in, slave out) pin . 16 pd.11 i/o general purpose digital i/o pin. mosi 30 i/o 1 st spi3 mosi (master out, slave in) pin . 17 pd.12 i/o general purpose digital i/o pin. miso 31 i/o 2 nd spi3 miso (master in, slave out) pin . 18 pd.13 i/o general purpose digital i/o pin. mosi 31 i/o 2 nd spi3 mosi (master out, slave in) pin . 19 10 8 pb.4 i/o general purpose digital i/o pin. rxd1 i data receiver input pin for uart1 . 20 11 9 pb.5 i/o general purpose digital i/o pin. txd1 o data transmitter output pin for uart1 . 21 12 pb.6 i/o general purpose digital i/o pin. rts1 o request to send output pin for uart1 . ale o ebi address latch enable output pin 22 13 pb.7 i/o general purpose digital i/o pin. cts1 i clear to send input pin for uart1 . ncs o ebi chip select enable output pin 23 14 10 ldo p ldo output pin 24 15 11 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 25 16 12 v ss p ground pin for digital circuit. 26 pe. 12 i/o general purpose digital i/o pin. 27 pe. 11 i/o general purpose digital i/o pin. 28 pe. 10 i/o general purpose digital i/o pin. 29 pe. 9 i/o general purpose digital i/o pin. 30 pe.8 i/o general purpose digital i/o pin. 31 pe.7 i/o general purpose digital i/o pin. 32 17 13 pb.0 i/o general purpose digital i/o pin. rxd0 i data receiver input pin for uart0 . 33 18 14 pb.1 i/o general purpose digital i/o pin. txd0 o data transmitter output pin for uart0 . 34 19 15 pb.2 i/o general purpose digital i/o pin. rts0 o request to send output pin for uart0 .
nuc100/120xxxdn aug 31 , 201 5 page 29 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin t2ex i timer2 external capture input pin . nwrl o ebi low byte write enable output pin 35 20 16 pb.3 i/o general purpose digital i/o pin. cts0 i clear to send input pin for uart0 . t3ex i timer3 external capture input pin . sc2 cd i smartcard 2 card detect pin . nwrh o ebi high byte write enable output pin 36 21 pd.6 i/o general purpose digital i/o pin. 37 22 pd.7 i/o general purpose digital i/o pin. 38 23 pd.14 i/o general purpose digital i/o pin. rxd2 i data receiver input pin for uart2 . 39 24 pd.15 i/o general purpose digital i/o pin. txd2 o data transmitter output pin for uart2 . 40 pc.5 i/o general purpose digital i/o pin. mosi 01 i/o 2 nd spi 0 mosi (master out, slave in) pin . 41 pc.4 i/o general purpose digital i/o pin. miso 01 i/o 2 nd spi 0 miso (master in, slave out) pin . 42 25 17 pc.3 i/o general purpose digital i/o pin. mosi 00 i/o 1 st spi 0 mosi (master out, slave in) pin . i2sdo o i 2 s data output . 43 26 18 pc.2 i/o general purpose digital i/o pin. miso 00 i/o 1 st spi 0 miso (master in, slave out) pin . i2sdi i i 2 s data input . 44 27 19 pc.1 i/o general purpose digital i/o pin. sp i clk0 i/o spi0 s erial clock pin . i2sbclk i/o i 2 s bit clock pin . 45 28 20 pc.0 i/o general purpose digital i/o pin. spiss 00 i/o 1 st spi0 slave select pin . i2slrclk i/o i 2 s left right channel clock . 46 pe.6 i/o general purpose digital i/o pin. 47 29 21 pe.5 i/o general purpose digital i/o pin. pwm 5 i/o pwm 5 output /capture input .
nuc100/120xxxdn aug 31 , 201 5 page 30 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin t1ex i timer1 external capture input pin. 48 30 22 pb.11 i/o general purpose digital i/o pin. tm3 i/o timer3 event counter input / toggle output . pwm 4 i/o pwm 4 output /capture input . 49 31 23 pb.10 i/o general purpose digital i/o pin. tm2 i/o timer2 event counter input / toggle output . spiss 01 i/o 2 nd spi0 slave select pin . 50 32 24 pb.9 i/o general purpose digital i/o pin. tm1 i/o timer1 event counter input / toggle output . spiss 11 i/o 2 nd spi1 slave select pin . 51 pe.4 i/o general purpose digital i/o pin. 52 pe.3 i/o general purpose digital i/o pin. 53 pe.2 i/o general purpose digital i/o pin. 54 pe.1 i/o general purpose digital i/o pin. pwm 7 i/o pwm 7 output /capture input . 55 pe.0 i/o general purpose digital i/o pin . pwm 6 i/o pwm 6 output /capture input . 56 pc.13 i/o general purpose digital i/o pin. mosi 11 i/o 2 nd spi 1 mosi (master out, slave in) pin . 57 pc.12 i/o general purpose digital i/o pin. miso 11 i/o 2 nd spi 1 miso (master in, slave out) pin . 58 33 pc.11 i/o general purpose digital i/o pin. mosi 10 i/o 1 st spi 1 mosi (master out, slave in) pin . 59 34 pc.10 i/o general purpose digital i/o pin. miso 10 i/o 1 st spi 1 miso (master in, slave out) pin . 60 35 pc.9 i/o general purpose digital i/o pin. sp i clk1 i/o spi1 s erial clock pin . 61 36 pc.8 i/o general purpose digital i/o pin. spiss 10 i/o 1 st spi1 slave select pin . mclk o ebi external clock output pin 62 37 25 pa.15 i/o general purpose digital i/o pin. pwm3 i/o pwm output /capture input .
nuc100/120xxxdn aug 31 , 201 5 page 31 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin i2smclk o i 2 s master clock output pin . sc2 pwr o smartcard 2 power pin . 63 38 26 pa.14 i/o general purpose digital i/o pin. pwm2 i/o pwm 2 output /capture input . sc2 rst o smartcard 2 reset pin . ad1 5 i/o ebi address/data bus bit1 5 64 39 27 pa.13 i/o general purpose digital i/o pin. pwm1 i/o pwm 1 output /capture input . sc2 clk o smartcard 2 clock pin . ad1 4 i/o ebi address/data bus bit1 4 65 40 28 pa.12 i/o general purpose digital i/o pin. pwm0 i/o pwm 0 output /capture input . sc2 dat o smartcard 2 data pin . ad1 3 i/o ebi address/data bus bit1 3 66 41 29 ice _ dat i/o serial wire debu g ger data pin 67 42 30 ice_c l k i serial wire debu g ger clock pin 68 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 69 v ss p ground pin for digital circuit. 70 43 31 av ss ap ground p in for analog circuit . 71 44 32 pa.0 i/o general purpose digital i/o pin. adc0 ai adc 0 analog input . sc0 pwr o smartcard 0 power pin . 72 45 33 pa.1 i/o general purpose digital i/o pin. adc1 ai adc 1 analog input . sc0 rst o smartcard 0 reset pin . ad12 i/o ebi address/data bus bit12 73 46 34 pa.2 i/o general purpose digital i/o pin. adc2 ai adc 2 analog input . sc0 clk o smartcard 0 clock pin . ad11 i/o ebi address/data bus bit11 74 47 35 pa.3 i/o general purpose digital i/o pin. adc3 ai adc 3 analog input .
nuc100/120xxxdn aug 31 , 201 5 page 32 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin sc0 dat o smartcard 0 data pin . ad10 i/o ebi address/data bus bit10 75 48 36 pa. 4 i/o general purpose digital i/o pin. adc4 ai adc 4 analog input . sc1 pwr o smartcard1 power pin . ad 9 i/o ebi address/data bus bit 9 76 49 37 pa.5 i/o general purpose digital i/o pin. adc5 ai adc 5 analog input . sc1 rst o smartcard1 reset pin . ad 8 i/o ebi address/data bus bit 8 77 50 38 pa.6 i/o general purpose digital i/o pin. adc6 ai adc 6 analog input . sc1 clk i/o smartcard1 clock pin . ad 7 i/o ebi address/data bus bit 7 78 51 39 pa.7 i/o general purpose digital i/o pin. adc7 ai adc 7 analog input . sc1 dat o smartcard1 data pin . spiss 2 1 i/o 2 nd spi2 slave select pin . ad 6 i/o ebi address/data bus bit 6 79 v ref ap v oltage reference input for adc . 80 52 40 av dd ap p ower supply for internal analog circuit . 81 pd.0 i/o general purpose digital i/o pin. spiss 20 i/o 1 st spi2 slave select pin . 82 pd.1 i/o general purpose digital i/o pin. sp i clk2 i/o spi2 s erial clock pin . 83 pd.2 i/o general purpose digital i/o pin. miso 20 i/o 1 st spi 2 miso (master in, slave out) pin . 84 pd.3 i/o general purpose digital i/o pin. mosi 20 i/o 1 st spi 2 mosi (master out, slave in) pin . 85 pd.4 i/o general purpose digital i/o pin. miso 21 i/o 2 nd spi 2 miso (master in, slave out) pin . 86 pd.5 i/o general purpose digital i/o pin. mosi 21 i/o 2 nd spi 2 mosi (master out, slave in) pin .
nuc100/120xxxdn aug 31 , 201 5 page 33 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 87 53 41 pc.7 i/o general purpose digital i/o pin. cpn0 ai comparator 0 n egative input pin . sc1 cd i smartcard1 card detect pin . ad 5 i/o ebi address/data bus bit 5 88 54 42 pc.6 i/o general purpose digital i/o pin. cpp0 ai comparator 0 p ositive input pin . sc0 cd i smartcard 0 card detect pin . ad 4 i/o ebi address/data bus bit 4 89 55 pc.15 i/o general purpose digital i/o pin. cpn1 ai comparator 1 n egative input pin . ad 3 i/o ebi address/data bus bit 3 90 56 pc.14 i/o general purpose digital i/o pin. cpp1 ai comparator1 p ositive input pin . ad 2 i/o ebi address/data bus bit 2 91 57 43 pb.15 i/o general purpose digital i/o pin. / int1 i external interrupt 1 input pin . t0ex i timer0 external capture input pin. 92 58 44 pf.0 i/o general purpose digital i/o pin. xt 1 _out o external 4~24 mhz ( high speed ) crystal output pin . 93 59 45 pf.1 i/o general purpose digital i/o pin. xt 1 _in i external 4~24 mhz ( high speed ) crystal input pin . 94 60 46 /reset i external reset input : active low , with an internal pull - up . s et this pin low reset chip to initial state . 95 61 v ss p ground pin for digital circuit. 96 62 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 97 pf.2 i/o general purpose digital i/o pin. ps2dat i/o ps/2 d ata pin . 98 pf.3 i/o general purpose digital i/o pin. ps2clk i/o ps/2 clock pin . 99 63 47 pv ss p pll ground . 100 64 48 pb.8 i/o general purpose digital i/o pin. stadc i adc external trigger input. tm0 i/o timer0 event counter input / toggle output . note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power
nuc100/120xxxdn aug 31 , 201 5 page 34 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 4.3.2 numicro ? nuc 1 20 pin description pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.15 i/o general purpose digital i/o pin. 2 pe.14 i/o general purpose digital i/o pin. 3 pe.13 i/o general purpose digital i/o pin. 4 1 pb.14 i/o general purpose digital i/o pin. / int0 i external interrupt 0 input pin . spiss 3 1 i/o 2 nd spi3 slave select pin . 5 2 pb.13 i/o general purpose digital i/o pin. cpo1 o comparator1 output pin . ad1 i/o ebi address/data bus bit1 6 3 1 pb.12 i/o general purpose digital i/o pin. cpo0 o comparator0 output pin clko o frequency divider output pin ad0 i/o ebi address/data bus bit0 7 4 2 x32o o external 32.768 khz low speed crystal output pin 8 5 3 x32i i external 32.768 khz low speed crystal input pin 9 6 4 pa.11 i/o general purpose digital i/o pin. i2c1scl i/o i 2 c 1 clock pin . nrd o ebi read enable output pin 10 7 5 pa.10 i/o general purpose digital i/o pin. i2c1sda i/o i 2 c 1 data input/output pin . nwr o ebi write enable output pin 11 8 6 pa.9 i/o general purpose digital i/o pin. i2c0scl i/o i 2 c0 clock pin . 12 9 7 pa.8 i/o general purpose digital i/o pin. i2c0sda i/o i 2 c0 data input/output pin . 13 pd.8 i/o general purpose digital i/o pin. spiss 30 i/o 1 st spi3 slave select pin . 14 pd.9 i/o general purpose digital i/o pin. sp i clk3 i/o spi3 serial clock pin . 15 pd.10 i/o general purpose digital i/o pin. miso 30 i/o 1 st spi3 miso (master in, slave out) pin . 16 pd.11 i/o general purpose digital i/o pin.
nuc100/120xxxdn aug 31 , 201 5 page 35 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin mosi 30 i/o 1 st spi3 mosi (master out, slave in) pin . 17 pd.12 i/o general purpose digital i/o pin. miso 31 i/o 2 nd spi3 miso (master in, slave out) pin . 18 pd.13 i/o general purpose digital i/o pin. mosi 31 i/o 2 nd spi3 mosi (master out, slave in) pin . 19 10 8 pb.4 i/o general purpose digital i/o pin. rxd1 i data receiver input pin for uart1 . 20 11 9 pb.5 i/o general purpose digital i/o pin. txd1 o data transmitter output pin for uart1 . 21 12 pb.6 i/o general purpose digital i/o pin. rts1 o request to send output pin for uart1 . ale o ebi address latch enable output pin 22 13 pb.7 i/o general purpose digital i/o pin. cts1 i clear to send input pin for uart1 . ncs o ebi chip select enable output pin 23 14 10 ldo p ldo output pin 24 15 11 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 25 16 12 v ss p ground pin for digital circuit. 26 pe.8 i/o general purpose digital i/o pin. 27 pe. 7 i/o general purpose digital i/o pin. 28 17 13 v bus usb power supply from usb host or hub . 29 18 14 v dd33 usb internal power regulator output 3.3v decoupling pin. 30 19 15 d - usb usb d ifferential s ignal d - . 31 20 16 d+ usb usb d ifferential s ignal d+ . 32 21 17 pb.0 i/o general purpose digital i/o pin. rxd0 i data receiver input pin for uart0 . 33 22 18 pb.1 i/o general purpose digital i/o pin. txd0 o data transmitter output pin for uart0 . 34 23 29 pb.2 i/o general purpose digital i/o pin. rts0 o request to send output pin for uart0 . t2ex i timer2 external capture input pin . nwrl o ebi low byte write enable output pin
nuc100/120xxxdn aug 31 , 201 5 page 36 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 35 24 20 pb.3 i/o general purpose digital i/o pin. cts0 i clear to send input pin for uart0 . t3ex i timer3 external capture input pin . sc2 cd i smartcard 2 card detect pin . nwrh o ebi high byte write enable output pin 36 pd.6 i/o general purpose digital i/o pin. 37 pd.7 i/o general purpose digital i/o pin. 38 pd.14 i/o general purpose digital i/o pin. rxd2 i data receiver input pin for uart2 . 39 pd.15 i/o general purpose digital i/o pin. txd2 o data transmitter output pin for uart2 . 40 pc.5 i/o general purpose digital i/o pin. mosi 01 i/o 2 nd spi 0 mosi (master out, slave in) pin . 41 pc.4 i/o general purpose digital i/o pin. miso 01 i/o 2 nd spi 0 miso (master in, slave out) pin . 42 25 21 pc.3 i/o general purpose digital i/o pin. mosi 00 i/o 1 st spi 0 mosi (master out, slave in) pin . i2sdo o i 2 s data output . 43 26 22 pc.2 i/o general purpose digital i/o pin. miso 00 i/o 1 st spi 0 miso (master in, slave out) pin . i2sdi i i 2 s data input . 44 27 23 pc.1 i/o general purpose digital i/o pin. sp i clk0 i/o spi0 s erial clock pin . i2sbclk i/o i 2 s bit clock pin . 45 28 24 pc.0 i/o general purpose digital i/o pin. spiss 00 i/o 1 st spi0 slave select pin . i2slrclk i/o i 2 s left right channel clock . 46 pe.6 i/o general purpose digital i/o pin. 47 29 pe.5 i/o general purpose digital i/o pin. pwm 5 i/o pwm 5 output /capture input . t1ex i timer1 external capture input pin. 48 30 pb.11 i/o general purpose digital i/o pin.
nuc100/120xxxdn aug 31 , 201 5 page 37 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin tm3 i/o timer3 event counter input / toggle output . pwm 4 i/o pwm 4 output /capture input . 49 31 pb.10 i/o general purpose digital i/o pin. tm2 i/o timer2 event counter input / toggle output . spiss 01 i/o 2 nd spi0 slave select pin . 50 32 pb.9 i/o general purpose digital i/o pin. tm1 i/o timer1 event counter input / toggle output . spiss 11 i/o 2 nd spi1 slave select pin . 51 pe.4 i/o general purpose digital i/o pin. 52 pe.3 i/o general purpose digital i/o pin. 53 pe.2 i/o general purpose digital i/o pin. 54 pe.1 i/o general purpose digital i/o pin. pwm 7 i/o pwm 7 output /capture input . 55 pe.0 i/o general purpose digital i/o pin . pwm 6 i/o pwm 6 output /capture input . 56 pc.13 i/o general purpose digital i/o pin. mosi 11 i/o 2 nd spi 1 mosi (master out, slave in) pin . 57 pc.12 i/o general purpose digital i/o pin. miso 11 i/o 2 nd spi 1 miso (master in, slave out) pin . 58 33 pc.11 i/o general purpose digital i/o pin. mosi 10 i/o 1 st spi 1 mosi (master out, slave in) pin . 59 34 pc.10 i/o general purpose digital i/o pin. miso 10 i/o 1 st spi 1 miso (master in, slave out) pin . 60 35 pc.9 i/o general purpose digital i/o pin. sp i clk1 i/o spi1 s erial clock pin . 61 36 pc.8 i/o general purpose digital i/o pin. spiss 10 i/o 1 st spi1 slave select pin . mclk o ebi external clock output pin 62 37 25 pa.15 i/o general purpose digital i/o pin. pwm3 i/o pwm output /capture input . i2smclk o i 2 s master clock output pin . sc2 pwr o smartcard 2 power pin .
nuc100/120xxxdn aug 31 , 201 5 page 38 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 63 38 26 pa.14 i/o general purpose digital i/o pin. pwm2 i/o pwm 2 output /capture input . sc2 rst o smartcard 2 reset pin . ad1 5 i/o ebi address/data bus bit1 5 64 39 27 pa.13 i/o general purpose digital i/o pin. pwm1 i/o pwm 1 output /capture input . sc2 clk o smartcard 2 clock pin . ad1 4 i/o ebi address/data bus bit1 4 65 40 28 pa.12 i/o general purpose digital i/o pin. pwm0 i/o pwm 0 output /capture input . sc2 dat o smartcard 2 data pin . ad1 3 i/o ebi address/data bus bit1 3 66 41 29 ice _ dat i/o serial wire debu g ger data pin 67 42 30 ice_c l k i serial wire debu g ger clock pin 68 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 69 v ss p ground pin for digital circuit. 70 43 31 av ss ap ground p in for analog circuit . 71 44 32 pa.0 i/o general purpose digital i/o pin. adc0 ai adc 0 analog input . sc0 pwr o smartcard 0 power pin . 72 45 33 pa.1 i/o general purpose digital i/o pin. adc1 ai adc 1 analog input . sc0 rst o smartcard 0 reset pin . ad12 i/o ebi address/data bus bit12 73 46 34 pa.2 i/o general purpose digital i/o pin. adc2 ai adc 2 analog input . sc0 clk o smartcard 0 clock pin . ad11 i/o ebi address/data bus bit11 74 47 35 pa.3 i/o general purpose digital i/o pin. adc3 ai adc 3 analog input . sc0 dat o smartcard 0 data pin . ad10 i/o ebi address/data bus bit10
nuc100/120xxxdn aug 31 , 201 5 page 39 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 75 48 36 pa. 4 i/o general purpose digital i/o pin. adc4 ai adc 4 analog input . sc1 pwr o smartcard1 power pin . ad 9 i/o ebi address/data bus bit 9 76 49 37 pa.5 i/o general purpose digital i/o pin. adc5 ai adc 5 analog input . sc1 rst o smartcard1 reset pin . ad 8 i/o ebi address/data bus bit 8 77 50 38 pa.6 i/o general purpose digital i/o pin. adc6 ai adc 6 analog input . sc1 clk i/o smartcard1 clock pin . ad 7 i/o ebi address/data bus bit 7 78 51 39 pa.7 i/o general purpose digital i/o pin. adc7 ai adc 7 analog input . sc1 dat o smartcard1 data pin . spiss 2 1 i/o 2 nd spi2 slave select pin . ad 6 i/o ebi address/data bus bit 6 79 v ref ap v oltage reference input for adc . 80 52 40 av dd ap p ower supply for internal analog circuit . 81 pd.0 i/o general purpose digital i/o pin. spiss 20 i/o 1 st spi2 slave select pin . 82 pd.1 i/o general purpose digital i/o pin. sp i clk2 i/o spi2 s erial clock pin . 83 pd.2 i/o general purpose digital i/o pin. miso 20 i/o 1 st spi 2 miso (master in, slave out) pin . 84 pd.3 i/o general purpose digital i/o pin. mosi 20 i/o 1 st spi 2 mosi (master out, slave in) pin . 85 pd.4 i/o general purpose digital i/o pin. miso 21 i/o 2 nd spi 2 miso (master in, slave out) pin . 86 pd.5 i/o general purpose digital i/o pin. mosi 21 i/o 2 nd spi 2 mosi (master out, slave in) pin . 87 53 41 pc.7 i/o general purpose digital i/o pin. cpn0 ai comparator 0 n egative input pin .
nuc100/120xxxdn aug 31 , 201 5 page 40 of 1 07 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin sc1 cd i smartcard1 card detect pin . ad 5 i/o ebi address/data bus bit 5 88 54 42 pc.6 i/o general purpose digital i/o pin. cpp0 ai comparator 0 p ositive input pin . sc0 cd i smartcard 0 card detect pin . ad 4 i/o ebi address/data bus bit 4 89 55 pc.15 i/o general purpose digital i/o pin. cpn1 ai comparator 1 n egative input pin . ad 3 i/o ebi address/data bus bit 3 90 56 pc.14 i/o general purpose digital i/o pin. cpp1 ai comparator1 p ositive input pin . ad 2 i/o ebi address/data bus bit 2 91 57 43 pb.15 i/o general purpose digital i/o pin. / int1 i external interrupt 1 input pin . t0ex i timer0 external capture input pin. 92 58 44 pf.0 i/o general purpose digital i/o pin. xt 1 _out o external 4~24 mhz ( high speed ) crystal output pin . 93 59 45 pf.1 i/o general purpose digital i/o pin. xt 1 _in i external 4~24 mhz ( high speed ) crystal input pin . 94 60 46 /reset i external reset input : active low , with an internal pull - up . s et this pin low reset chip to initial state . 95 61 v ss p ground pin for digital circuit. 96 62 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 97 pf.2 i/o general purpose digital i/o pin. ps2dat i/o ps/2 d ata pin . 98 pf.3 i/o general purpose digital i/o pin. ps2clk i/o ps/2 clock pin . 99 63 47 pv ss p pll ground . 100 64 48 pb.8 i/o general purpose digital i/o pin. stadc i adc external trigger input. tm0 i/o timer0 event counter input / toggle output . note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power
nuc100/120xxxdn aug 31 , 201 5 page 41 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 5 block diagram numicro ? nuc 1 00 block diagram 5.1 figure 5 - 1 numicro ? nuc 1 00 block diagram a r m c o r t e x - m 0 5 0 m h z m e m o r y p d m a a p r o m 1 2 8 / 6 4 / 3 2 k b d a t a f l a s h 4 k b s r a m 1 6 / 8 / 4 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 r t c p w m / c a p t u r e t i m e r x 8 w a t c h d o g t i m e r 1 2 - b i t a d c x 8 p o w e r c o n t r o l c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l o s c . 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 3 s p i x 4 i 2 c x 2 p s / 2 i 2 s s c x 3 i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a n a l o g c o m p a r a t o r x 2 l o w s p e e d c r y s t a l o s c . 3 2 . 7 6 8 k h z l d r o m 4 k b a h b b u s a p b b u s b r i d g e e b i
nuc100/120xxxdn aug 31 , 201 5 page 42 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet numicro ? nuc 1 20 block diagram 5.2 figure 5 - 2 numicro ? nuc 1 20 block diagram a r m c o r t e x - m 0 5 0 m h z m e m o r y a p r o m 1 2 8 / 6 4 / 3 2 k b d a t a f l a s h 4 k b s r a m 1 6 / 8 / 4 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 r t c p w m / c a p t u r e t i m e r x 8 w a t c h d o g t i m e r 1 2 - b i t a d c x 8 p o w e r c o n t r o l c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l o s c . 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 3 s p i x 4 i 2 c x 2 p s / 2 i 2 s s c x 3 i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a n a l o g c o m p a r a t o r x 2 l o w s p e e d c r y s t a l o s c . 3 2 . 7 6 8 k h z u s b l d r o m 4 k b u s b p h y a h b b u s a p b b u s b r i d g e p d m a e b i
nuc100/120xxxdn aug 31 , 201 5 page 43 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6 functional d escription arm ? cortex ? - m0 core 6.1 the cortex ? - m0 processor is a configurable, multistage, 32 - bit r isc processor , which has an amba ah b - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex ? - m profil e processor. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an ex ception return. figure 6 - 1 shows the functional controller of processor. figure 6 - 1 functional controller diagram t he implemented device provides the following components and features : ? a low gate count processor: C armv6 - m thumb ? instruction set C thumb - 2 technology C armv6 - m compliant 24 - bit systick timer C a 32 - bit hardware multiplier C s ystem interface suppo rt ed with little - endian data accesses C a b ility to have deterministic, fi xed - latency, interrupt handling C load/store - multiples and multicycle - multiplies that can be abandoned and restarted to faci litate rapid i nterrupt handling C c application binary interface compliant exception model. this is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers C low p ower s leep mode entry using wait for interrupt (wfi), wait for even t (wfe) instructions, or the return from interrupt sleep - on - exit feature ? nvic: c o r t e x ? - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x ? - m 0 p r o c e s s o r c o r t e x ? - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
nuc100/120xxxdn aug 31 , 201 5 page 44 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C 32 external interrupt inputs, each with four levels of priority C dedicated non - m askable interrupt (nmi) input C support s for both level - sensitive and pulse - sensitive interrupt lines C supports wake - up interrupt controller (wic) and , providing u ltra - low p ower s leep mode ? d ebug support C four hardware breakpoints C two watchpoints C program counter sampling register (pcsr) for non - intrusive code profiling C single step and vector catch capabilities ? bus interfaces: C single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory C single 32 - bit slave port that supports the dap (debug access port)
nuc100/120xxxdn aug 31 , 201 5 page 45 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet system manager 6.2 6.2.1 overview the system manager provides the functions of system control, power modes, wake - up sources, reset sources, system memory map, product id and multi - function pin control. the following sections describe the functions for ? system reset ? system power architecture ? system memory map ? system management registers for part number id , chip reset and on - chip controllers reset, and multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control registe rs 6.2.2 system reset the system reset can be issued by one of the events listed below. these reset event flags can be read from rst s rc register to determine the reset source. hardware reset can reset chip through peripheral reset signals. software reset can tri gger reset through control registers. ? hardware reset sources C power - on reset (por) C low level on the nreset pin C watchdog time - out reset and window watchdog reset (wdt/wwdt reset) C low voltage reset (lvr) C brown - out detector reset (bod reset) ? software reset sources C chip reset will reset whole chip by writing 1 to chip _ rst ( iprstc1[0] ) C mcu reset to reboot but keeping the booting setting from aprom or ldrom by writing 1 to sysresetreq ( aircr[2] ) C cpu reset for cortex ? - m 0 core only by writing 1 to cpu _ rst ( iprstc1[1] ) power - o n reset or chip_rst (iprst c 1 [0]) reset the whole chip including all peripherals , external crystal circuit and bs (ispcon[1]) bit . sysresetreq ( aircr[2] ) reset the whole chip including all peripherals , but does not reset external crystal circuit and bs (ispcon[1]) bit .
nuc100/120xxxdn aug 31 , 201 5 page 46 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet figure 6 - 2 system reset resources there are a total of 8 reset sources in the numicro ? family. in general, cpu reset is used to reset cortex ? - m 0 only; the other re set sources will reset cortex ? - m 0 and all peripherals. however, there are small differences between each reset source and they are listed in table 6 - 1 . reset sources register por nreset wdt lvr bod chip mcu cpu rstsrc bit 0 = 1 bit 1 = 1 bit 2 = 1 bit 3 = 1 bit 4 = 1 bit 0 = 1 bit 5 = 1 bit 7 = 1 chip _ rst (iprst c1 [0]) 0x0 - - - - - - - bod _ en (bodcr[0]) reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 reload from config0 - bod _ vl (bodcr[2:1]) bod _ rsten (bodcr[3]) xtl12m_en ( pwrcon [0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - wdt_en (apbclk[0]) 0x1 - 0x1 - - 0x1 - - hclk _ s (clksel0[2:0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - wdt _ s 0x3 0x3 - - - - - - l o w v o l t a g e r e s e t p o w e r - o n r e s e t b r o w n - o u t r e s e t r e s e t p u l s e w i d t h 3 . 2 m s w d t / w w d t r e s e t ~ 5 0 k o h m @ 5 v r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s n r e s e t v d d a v d d c h i p r e s e t c h i p _ r s t ( i p r s t c 1 [ 0 ] ) c p u r e s e t c p u _ r s t ( i p r s t c 1 [ 1 ] ) m c u r e s e t s y s r e s e t r e q ( a i r c r [ 2 ] ) b o d _ r s t e n ( b o d c r [ 3 ] ) r e s e t p u l s e w i d t h 6 4 w d t c l o c k s g l i t c h f i l t e r 3 6 u s s o f t w a r e r e s e t l v r _ e n ( b o d c r [ 7 ] ) p o r _ d i s _ c o d e ( p o r c r [ 1 5 : 0 ] ) s y s t e m r e s e t
nuc100/120xxxdn aug 31 , 201 5 page 47 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet (clksel1[1:0]) xtl12m_stb (clkstatus[0]) 0x0 - - - - - - - xtl 32k _stb (clkstatus[ 1 ]) 0x0 - - - - - - - pll _ stb (clkstatus[2]) 0x0 - - - - - - - osc10k _ stb (clkstatus[ 3 ]) 0x0 - - - - - - - osc22m _ stb (clkstatus[4]) 0x0 - - - - - - - clk_sw_fail (clkstatus[7]) 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - wte (w tcr [7]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - - wtcr 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - wtcralt 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - wwdtrld 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - wwdtcr 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 - - wwdtsr 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - wwdtcvr 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f - - bs (ispcon[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - - dfbadr reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 - - cbs (ispsta[2:1)) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - - vecmap (ispsta[2 0 :9]) reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 - - other peripheral registers reset value - fmc registers reset value note: - means that the value of register keeps original setting. table 6 - 1 reset value of registers
nuc100/120xxxdn aug 31 , 201 5 page 48 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet nreset reset 6.2.2.1 the nreset reset means to generate a reset signal by pull ing low nreset pin , which is an asynchronous reset input pin and can be used to reset system at any time. when the nreset volt age is lower than 0.2 v dd and the state keeps longer than 36 us (glitch filter ), c hip will be reset. the nreset reset will control the chip in reset state until the nreset voltage rises above 0.7 v dd and the state keeps longer than 36 us ( glitch filter). the rsts_reset ( rstsrc [1]) will be set to 1 if the previous reset source is nreset reset. figure 6 - 3 shows the nreset reset waveform. figure 6 - 3 nreset reset waveform power - on reset (por) 6.2.2.2 the power - on reset (por) is used to generate a stable system reset signal and forces the system to be reset when p ower - on to avoid unexpected behavior of mcu. when applying the power to mcu, the por module will detect the rising voltage and generate reset signal to system until the voltage is ready for mcu operation. at por reset, the rsts_por ( rstsrc [0]) will be set to 1 to indicate there is a por reset event. the rsts_por ( rstsrc [0]) bit can be cleared by writing 1 to it . figure 6 - 4 shows the waveform of power - on reset . figure 6 - 4 power - on reset (por) waveform l ow voltage reset (lvr) 6.2.2.3 if the low voltage reset function is enabled by setting the low voltage reset enable bit lvr _ en (bodcr[7]) to 1, after 1 00us delay, lvr detection circuit will be stable and the lvr function will be active. then lvr function will detect av dd dur ing system operation. when the s s n r e s e t 0 . 2 v d d 0 . 7 v d d n r e s e t r e s e t s s 3 6 u s 3 6 u s v d d v p o r p o w e r o n r e s e t 0 . 1 v
nuc100/120xxxdn aug 31 , 201 5 page 49 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet av dd voltage is lower than v lvr and the state keeps longer than de - glitch time (16*hclk cycles) , c hip will be reset. the lvr reset will control the chip in reset state until the av dd voltage rises above v lvr and the state keeps longer than de - glitch time . the rsts_reset ( rstsrc [1]) will be set to 1 if the previous reset source is nreset reset. figure 6 - 5 shows the low v oltage reset waveform . figure 6 - 5 low voltage reset (lvr) waveform brown - out detector reset (bod reset) 6.2.2.4 if the brown - o ut detector (bod) function is enabled by setting the brown - o ut detector enable bit bod _ en ( bodcr [0]), brown - out detector function will detect av dd during system operation. when the av dd voltage is lower than v bod which is decided by bod _ en ( bodcr [0]) and bod _ vl (bodc r [2:1]) and the state keeps longer than de - glitc h time (max(20*hclk cycles, 1*lirc cycle)) , c hip will be reset. the bod reset will control the chip in reset state until the av dd voltage rises above v bod and the state keeps longer than de - glitch time . the default value of bod _ en, bod _ vl and bod _ rsten is set by flash controller user configuration register cboden (config0[23]), cbov1 - 0 (config0[22:21]) and cborst (config0[20]) respectively. user can determine the initial bod setting by setting the config0 register . figure 6 - 6 shows the brown - out detector waveform . a v d d v l v r l o w v o l t a g e r e s e t t 1 ( < d e - g l i t c h t i m e ) t 2 ( = d e - g l i t c h t i m e ) t 3 ( = d e - g l i t c h t i m e ) l v r _ e n 1 0 0 u s d e l a y f o r l v r s t a b l e
nuc100/120xxxdn aug 31 , 201 5 page 50 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet figure 6 - 6 brown - out detector (bod) waveform watch d og timer reset 6.2.2.5 in most industrial applications, system reliability is very important. to automatically recover the mcu from failure status is one way to improve system reliability. the watchdog timer (wdt) is widely used to check if the system works fine. if the mcu is cras hed or out of control, it may cause the watchdog time - out. user may decide to enable system reset during watchdog time - out to recover the system and take action for the system crash/out - of - control after reset. software can check if the reset is caused by watchdog time - out to indicate the previous reset is a watchdog reset and handle the failure of mcu after watchdog time - out reset by checking rsts_wdt (rstsrc[2]). cpu reset, chip reset and mcu reset 6.2.2.6 the cpu reset means only cortex ? - m 0 core is reset and al l other peripherals remain the same status after cpu reset. user can set the cpu reset cpu_rst (iprstc1[1]) to 1 to assert the cpu reset signal. the chip reset is same with power - on reset. the cpu and all peripherals are reset and bs (ispcon[1]) bit is aut omatically reloaded from config 0 setting. user can set the chip reset chip_rst (iprstc1[0]) to 1 to assert the chip reset signal. the mcu reset is similar with chip reset. the difference is that bs (ispcon[1]) will not be reloaded from config 0 setting and keep its original software setting for booting from ap rom or ldrom. user can set the mcu reset sysresetreq(aircr[2]) to 1 to assert the mcu reset. a v d d v b o d l b o d o u t b o d r s t e n b r o w n - o u t r e s e t t 1 ( < d e - g l i t c h t i m e ) t 2 ( = d e - g l i t c h t i m e ) t 3 ( = d e - g l i t c h t i m e ) h y s t e r e s i s v b o d h
nuc100/120xxxdn aug 31 , 201 5 page 51 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.2.3 power m odes and wake - up s ources there are several wake - up sources in i dle mode and p ower - down mode. table 6 - 2 lists the available clocks for each power mode. power mode normal m ode idle m ode power - down m ode definition cpu is in active state cpu is in sleep state cpu is in sleep state and all clocks stop except lxt and lirc. sram content retended. entry condition c hip is in normal mode after system reset released cpu executes wfi instruction. cpu sets sleep mode enable and power down enable and executes wfi instr uction. wake - up sources n/a all interrupts rtc, wdt, i2c, timer, uart, bod , usb and gpio available clocks all all except cpu clock lxt and lirc after wake - up n/a cpu back to normal mode cpu back to normal mode table 6 - 2 power mode difference table figure 6 - 7 power mode state machine 1 . l xt ( 32 k hz xtl) on or off depend s on s/w setting in run mode . 2. lirc (10 khz osc) on or off depend s on s/w setting in run mode . n o r m a l m o d e c p u c l o c k o n h x t , l x t , h i r c , l i r c , h c l k , p c l k o n f l a s h o n p o w e r - d o w n m o d e c p u c l o c k o f f h x t , h i r c , h c l k , p c l k o f f f l a s h h a l t s y s t e m r e s e t r e l e a s e d c p u e x e c u t e s w f i i n t e r r u p t s o c c u r i d l e m o d e c p u c l o c k o f f h x t , l x t , h i r c , l i r c , h c l k , p c l k o n f l a s h h a l t 1 . s l e e p d e e p ( s c r [ 2 ] ) = 1 2 . p w r _ d o w n _ e n ( p w r c o n [ 7 ] ) = 1 p d _ w a i t _ c p u ( p w r c o n [ 8 ] ) = 1 3 . c p u e x e c u t e s w f i w a k e - u p e v e n t s o c c u r l x t , l i r c o n
nuc100/120xxxdn aug 31 , 201 5 page 52 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 3 . if timer clock source is selected as lxt/ lirc and lxt/ lirc is on. 4 . if pwm clock source is selected as lxt and lxt is on. 5. if wdt clock source is selected as lxt/ lirc and lxt/ lirc is on. 6. if rtc cl ock source lxt is on. normal mode idle mode power - down mode hxt (4~20 mhz xtl) on on halt hirc (12 /16 mhz osc) on on halt l xt ( 32 k hz xtl) on on on/off 1 lirc (10 khz osc) on on on/off 2 pll on on halt ldo on on on cpu on halt halt hclk/pclk on on halt sram retention on on on flash on on halt ebi on on halt gpio on on halt pdma on on halt t i m e r on on on/off 3 pwm on on on/off 4 wdt on on on/off 5 wwdt on on halt rtc on on on/off 6 uart on on halt sc on on halt ps/2 on on halt i 2 c on on halt spi on on halt i 2 s on on halt usb on on halt adc on on halt acmp on on halt table 6 - 3 c lock s in power modes wake - up sources in p ower - down mode : wdt, i2c, timer , rtc , uart, bod , gpio and usb
nuc100/120xxxdn aug 31 , 201 5 page 53 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet after chip enters power down, the following wake - up sources can wake chip up to n ormal mode . wake - up source wake - up condition system can enter power - down mode again condition* bod brown - out detector interrupt after software writes 1 to clear bod_intf (bodcr [ 4 ] ) . gpio gpio interrupt after software write 1 to clear the isrc[n] bit. timer timer interrupt after software writes 1 to clear twf ( tisr x [1]) and t i f ( tisr x [0]) . wdt wdt interrupt after software writes 1 to clear wtwkf ( wtcr [5]) (write protect). rtc alarm interrupt afte r software writes 1 to clear a if (riir[0]). time tick interrupt afte r software writes 1 to clear t if (riir[1]). uart ncts wake - up a fter software writes 1 to clear dctsf ( ua_msr [ 0 ]) . i 2 c a ddressing i 2 c device after software writes 1 to clear wkupif ( i2cwkupsts [0]). usb remote wake - up after software writes 1 to clear bus_sts ( usbd_intsts [0]). *user needs to wait this condition before setting pwr_down_en (pwrcon[7]) and execute wfi to enter power - down mode. table 6 - 4 *user needs to wait this condition before setting pwr_down_en (pwrcon[7]) and execute wfi to enter power - down mode. table 6 - 4 list s the condition about how to enter p ow er - down mode again for each peripheral. wake - up source wake - up condition system can enter power - down mode again condition* bod brown - out detector interrupt after software writes 1 to clear bod_intf (bodcr [ 4 ] ) . gpio gpio interrupt after software write 1 to clear the isrc[n] bit. timer timer interrupt after software writes 1 to clear twf ( tisr x [1]) and t i f ( tisr x [0]) . wdt wdt interrupt after software writes 1 to clear wtwkf ( wtcr [5]) (write protect). rtc alarm interrupt afte r software writes 1 to clear a if (riir[0]). time tick interrupt afte r software writes 1 to clear t if (riir[1]). uart ncts wake - up a fter software writes 1 to clear dctsf ( ua_msr [ 0 ]) . i 2 c a ddressing i 2 c device after software writes 1 to clear wkupif ( i2cwkupsts [0]). usb remote wake - up after software writes 1 to clear bus_sts ( usbd_intsts [0]). *user needs to wait this condition before setting pwr_down_en (pwrcon[7]) and execute wfi to enter power - down mode. table 6 - 4 condition of entering power - down mode again 6.2.4 system power distribution in this chip , the power distribution is divided into three segments. ? analog power from av dd and av ss provides the power for analog components operation. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins.
nuc100/120xxxdn aug 31 , 201 5 page 54 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet ? usb transceiver power from v bus offers the power for operating the usb transceiver. the outputs of internal voltage regulators, ldo and v dd33 , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). figure 6 - 8 shows the power distribution of numicro ? nuc 1 0 0 . figure 6 - 9 shows the power distribution of numicro ? nuc1 2 0 . figure 6 - 8 numicro ? nuc 1 0 0 power distribution diagram l d o p l l 1 2 - b i t s a r - a d c b r o w n o u t d e t e c t o r p o r 5 0 p o r 1 8 l o w v o l t a g e r e s e t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s v d d v s s l d o 1 u f i o c e l l g p i o x 3 2 o x 3 2 i p v s s n u c 1 0 0 p o w e r d i s t r i b u t i o n
nuc100/120xxxdn aug 31 , 201 5 page 55 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet figure 6 - 9 numicro ? nuc1 2 0 power distribution diagram l d o u s b 1 . 1 t r a n c e i v e r 5 v t o 3 . 3 v l d o p l l 1 2 - b i t s a r - a d c b r o w n o u t d e t e c t o r p o r 5 0 p o r 1 8 l o w v o l t a g e r e s e t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c 3 . 3 v 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s v d d v s s v b u s v d d 3 3 d + d - l d o 1 u f 1 u f i o c e l l g p i o x 3 2 o x 3 2 i p v s s n u c 1 2 0 p o w e r d i s t r i b u t i o n
nuc100/120xxxdn aug 31 , 201 5 page 56 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.2.5 system memory map the numicro ? nuc1 00 s eries provides 4g - byte address ing space. the memory locations assigned to each on - chip controllers are shown in the following table. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip peripheral . the numicro ? nuc1 00 s eries only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x0001_ffff flash_ba flash memory space (128 kb) 0x2000_0000 C 0x2000_3fff sram_ba sram memory space (16 kb) ahb controllers space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog timer control registers 0x4000_8000 C 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 C 0x4001_3fff tmr0 1 _ba timer0 /timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi 1 _ba spi 1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwma_ba pwm0 /1/2/3 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x400d_0000 C 0x400d_3fff acmp_ba analog comparator control registers 0x400e_0000 C 0x400e_ffff adc_ba analog - digital - converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 C 0x4010_3fff ps2_ba ps / 2 interface control registers 0x4011_0000 C 0x4011_3fff tmr2 3 _ba timer2 /timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 C 0x4013_3fff spi 2 _ba spi 2 with master/slave function control r egisters 0x4013_4000 C 0x4013_7fff spi 3 _ba spi3 with master/s lave function control registers 0x40 1 4_0000 C 0x40 1 4_3fff pwmb_ba pwm 4/5/6/7 control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers
nuc100/120xxxdn aug 31 , 201 5 page 57 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 0x4015_ 4 000 C 0x4015_ 7 fff uart 2 _ba uart 2 control registers 0x40 19 _0000 C 0x40 19 _3fff sc 0_ba sc 0 control registers 0x40 19 _ 4 000 C 0x40 19 _ 7 fff sc1 _ba sc1 control registers 0x40 19 _ 8 000 C 0x40 19 _ b fff sc2 _ba sc2 control registers 0x40 1 a_0000 C 0x40 1 a_3fff i2s_ba i 2 s interface control registers system controllers space (0x e000 _ e 000 ~ 0x e000 _ e fff) 0x e000 _ e 0 1 0 C 0x e000 _ e0 ff scs_ba system timer control registers 0x e000 _ e10 0 C 0x e000 _ ec ff scs_ba external interrupt controller control registers 0x e000 _ ed0 0 C 0x e000 _ ed8 f scs_ba system control registers table 6 - 5 address space assignments for on - chip controllers
nuc100/120xxxdn aug 31 , 201 5 page 58 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.2.6 system timer (systick) the cortex ? - m0 includes an integrated system timer, systick , which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count d own from the value in the systick current value register (syst_cvr) to 0 , and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle , then decrement on subsequent clocks. when the counter transitions to 0 , the co untflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to 0 before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is 0 , the timer will be maintained with a current value of 0 after it is reloaded with this value. t his mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
nuc100/120xxxdn aug 31 , 201 5 page 59 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.2.7 nested vectored inte rrupt controller (nvic) the cortex ? - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic) , which is closely coupled to the processor core and provides following features: ? neste d and vectored interrupt support ? automatic processor state saving and restoration ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when a n interrupt is accepted, the starting address of the interrupt service routine ( isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processo r state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also support s late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the hig her one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
nuc100/120xxxdn aug 31 , 201 5 page 60 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet clock controller 6.3 6.3.1 overview the clock controller generates the clock s for the whole chip , includ ing system clocks and all peripheral clocks . the clock controller also implements the power control function with the individually clock on/off control, clock source select ion and clock divider . the chip enters power - down mode when cortex ? - m0 core execute s the wfi i nstruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1 . after that, chip enter s p ower - down mode and wait s for wake - up interrupt source trig gered to leave p ower - down mode. i n the p ower - down mode, the clock controller turn s off the external 4~24 mhz high speed crystal and internal 22 .1184 mhz high speed oscillator to reduce the overall system power consumption.
nuc100/120xxxdn aug 31 , 201 5 page 61 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet figure 6 - 10 clock g enerator g lobal v iew d iagram 1 0 p l l c o n [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 0 a d c u a r t 0 - 2 p d m a a c m p i 2 c 0 ~ 1 i 2 s r t c p w m 0 - 1 w d t p w m 2 - 3 p w m 4 - 5 p w m 6 - 7 t m r 3 t m r 2 t m r 1 c p u f m c 3 2 . 7 6 8 k h z 1 0 k h z 0 1 1 0 1 0 0 0 1 0 0 0 h c l k 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z 2 2 . 1 1 8 4 m h z 0 0 0 c l k s e l 0 [ 2 : 0 ] s y s t _ c s r [ 2 ] c p u c l k 1 / ( h c l k _ n + 1 ) p c l k c p u c l k h c l k 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 1 [ 3 : 2 ] e x t e r n a l t r i g g e r c l k s e l 1 [ 2 2 : 2 0 ] c l k s e l 1 [ 1 8 : 1 6 ] c l k s e l 1 [ 1 4 : 1 2 ] c l k s e l 1 [ 1 0 : 8 ] 1 1 1 0 0 1 0 0 h c l k p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 0 1 1 0 1 0 0 0 1 0 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z w w d t 1 0 k h z 1 / ( a d c _ n + 1 ) c l k s e l 2 [ 1 : 0 ] 1 1 1 0 c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t _ n + 1 ) 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z 0 1 3 2 . 7 6 8 k h z 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z c l k s e l 1 [ 2 5 : 2 4 ] 2 2 . 1 1 8 4 m h z 1 0 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 3 [ 5 : 4 ] 2 2 . 1 1 8 4 m h z 1 0 s c 2 1 / ( s c 2 _ n + 1 ) c l k s e l 3 [ 3 : 2 ] c l k s e l 3 [ 1 : 0 ] s c 1 1 / ( s c 1 _ n + 1 ) s c 0 1 / ( s c 0 _ n + 1 ) 1 0 k h z 2 2 . 1 1 8 4 m h z 1 0 1 1 1 1 1 0 s p i 0 - 3 s y s t _ c s r [ 2 ] c p u c l k u s b 1 / ( u s b _ n + 1 ) p l l f o u t 1 1 1 0 0 1 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z c l k s e l 2 [ 3 : 2 ] f d i v b o d 1 0 k h z 1 1 1 0 c l k s e l 2 [ 1 7 : 1 6 ] 1 0 k h z c l k s e l 2 [ 1 1 : 4 ] c l k s e l 1 [ 3 1 : 2 8 ] 1 0 k h z 1 1 1 p s 2 2 2 . 1 1 8 4 m h z e b i n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
nuc100/120xxxdn aug 31 , 201 5 page 62 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.3.2 clock generator the clock generator consists of 5 clock sources as list ed below: ? one external 32 .768 khz low speed crystal ? one external 4~24 mhz high speed crystal ? one programmable pll fout (pll source consists of external 4~24 m hz high speed crystal and internal 22 .1184 m hz high speed oscillator ) ? one internal 2 2 .1184 mhz high speed oscillator ? one internal 10 khz low speed oscillator figure 6 - 11 clock g enerator b lock d iagram x t _ o u t e x t e r n a l 4 ~ 2 4 m h z c r y s t a l x t l 1 2 m _ e n ( p w r c o n [ 0 ] ) x t _ i n i n t e r n a l 2 2 . 1 1 8 4 m h z o s c i l l a t o r o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 0 1 p l l p l l _ s r c ( p l l c o n [ 1 9 ] ) p l l f o u t x 3 2 o e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l 3 2 . 7 6 8 k h z x t l 3 2 k _ e n ( p w r c o n [ 1 ] ) x 3 2 i i n t e r n a l 1 0 k h z o s c i l l a t o r o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 1 0 k h z
nuc100/120xxxdn aug 31 , 201 5 page 63 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.3.3 system clock and systick clock the system clock has 5 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_ s ( clksel0[2:0]). the block diagram is show n in figure 6 - 12 . figure 6 - 12 system clock block diagram the clock source of systick in cortex ? - m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3] ) . the block diagram is show n in figure 6 - 13 . figure 6 - 13 systick c lock control block diagram 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) 2 2 . 1 1 8 4 m h z 0 0 0 1 / ( h c l k _ n + 1 ) h c l k _ n ( c l k d i v [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k p c l k n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e . 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
nuc100/120xxxdn aug 31 , 201 5 page 64 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.3.4 peripherals clock the peripherals clock can be selected as different clock source depends on the clock source select control registers ( clksel1 , clksel2 and clksel3) . 6.3.5 power - d own m ode clock when chip enters p ower - down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock s are still active in p ower - down mode. the clocks still kep t active are list ed below: ? clock generator ? internal 10 khz low speed oscillator clock ? external 32 .768 khz low speed crystal clock ? peripherals clock ( w hen ip adopt external 32 .768 khz low speed crystal oscillator or 10 k hz low speed oscillator as clock source) 6.3.6 frequency divi der output this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 1 6 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clo ck divider output frequency and n is the 4 - bit value in fse l ( frqdiv[3:0] ) . when writ ing 1 to divider_en (frqdiv[4]), the chained counter starts to count. when writ ing 0 to divider_en (frqdiv[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. figure 6 - 14 clock source of fr e quency divider 1 1 1 0 0 1 0 0 h c l k 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z f r q d i v _ s ( c l k s e l 2 [ 3 : 2 ] ) f d i v _ e n ( a p b c l k [ 6 ] ) f r q d i v _ c l k n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
nuc100/120xxxdn aug 31 , 201 5 page 65 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet figure 6 - 15 frequency divider block diagram 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f s e l ( f r q d i v [ 3 : 0 ] ) c l k o f r q d i v _ c l k 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r d i v i d e r _ e n ( f r q d i v [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r
nuc100/120xxxdn aug 31 , 201 5 page 66 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet flash memory controller (fmc) 6.4 6.4.1 overview the numicro ? nuc1 00 s eries has 128/64/32 kbytes on - chip embedded flash for application program memory (aprom) that can be updated through isp procedure. the i n - system - programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip is power ed on, cortex ? - m0 cpu fetc hes code from aprom or ldrom decided by boot select (cbs) in config0. by the way, the numicro ? nuc1 00 s eries also provides additional data flash for user to store some application dependent data. for 128 kbytes aprom device, the data flash is shared with original 128k program memory and its start address is configurable in config1. for 64/32 kbytes aprom device, the data flash is fixed at 4k. 6.4.2 features ? run s up to 50 mhz with zero wait state for continuous address read access ? all embedded flash memory supports 512 bytes page erase ? 128/64/32 kb application program memory (aprom) ? 4 kb i n - s ystem - p rogramming (isp) loader program memory (ldrom) ? 4kb data flash for 64/32 kb aprom device ? configurable data flash size for 128kb aprom device ? configura ble or fixed 4 kb data flash with 512 bytes page erase unit ? support s in - application - programming (iap) to switch code between aprom and ldrom without reset ? in - system - program ming (isp) to update on - chip flash
nuc100/120xxxdn aug 31 , 201 5 page 67 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet external bus interface (ebi) 6.5 6.5.1 overview the numicro ? nuc1 00 series lqfp - 64 and lqfp - 100 package is equip ped with an external bus interface (ebi) for access ing an external device. to save the connections between external device and this chip, ebi support s address bus and data bus multiplex mode. and, address latch enable (ale) signal is used to differentiate the address and data cycle. 6.5.2 features external bus interface has the following functions: ? supports e xternal devices with max. 64 k b size (8 - bit data wi dth)/128 k b (16 - bit data width) ? supports v ariable external bus base clock (mclk) which based on hclk ? supports 8 - bit or 16 - bit data width ? supports v ariable data access time (tacc), address latch enable time (tale) and address hold time (tahd) ? supports a ddre ss bus and data bus multiplex mode to save the address pins ? supports c onfigurable idle cycle for different access condition: write command finish (w2x), read - to - read (r2r)
nuc100/120xxxdn aug 31 , 201 5 page 68 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet general purpose i/o (gpio) 6.6 6.6.1 overview the numicro ? nuc1 0 0 series has u p to 8 4 general purpose i/o pins to be shared with other function pins depend ing on the chip configuration. these 84 pins are arranged in 6 ports named as gpioa, gpiob, gpioc, gpiod, gpioe and gpiof . the gpioa/b/c/d/e port has the maximum of 16 pins and gpiof port has the maximum of 4 pins . each o f the 8 4 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, output, o pen - drain or q uasi - bidirectional mode. after reset, the i/o mode of all pins are depending on config0[10] setting . in quasi - bidirectional mode, i/o pin has a very weak individual pull - up resistor which is about 110~300 k ? for v dd is from 5.0 v to 2.5 v. 6.6.2 features ? four i/o modes: C quasi - bidirection al C push - pull output C open - drain output C input only with high impendence ? ttl/schmitt trigger input selectable by gpx_type[15:0] in gpx_mfp[ 31 : 16 ] ? i/o pin configured as interrupt source with edge/level setting ? configurable default i/o mode of all pins after reset by config0[10] setting C if config[10] is 0, all gpio pins in input tri - state mode after chip reset C if config[10] is 1, all gpio pins in q uasi - bidirectional mode after chip reset ? i/o pin internal pull - up resistor enabled only in q uasi - bidirectional i/o mode ? enabl ing the pin interrupt function will also enable the pin wake - up function .
nuc100/120xxxdn aug 31 , 201 5 page 69 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet p dma controller ( p dma) 6.7 6.7.1 overview the numicro ? nuc1 00 series dma contains nine - channel peripheral direct memory access (pdma) controller and a cyclic redundancy check (crc) generator. the pdma that transfers data to and from memory or transfer data to and from apb devices. for pdma channel (pdma ch0~ch8), there is one - word buffer as transfer buffer between the peripherals apb devices and memory. software can stop the pdma operation by disable pdma pdma_csrx [pdmacen]. the cpu can recognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. the pdma controller can increase s ource or destination address or fixed them as well. the dma controller contains a cyclic redundancy check (crc) generator that can perform crc calculation with programmable polynomial settings. the crc engine support s cpu pio mode and dma transfer mode. 6.7.2 fe atures ? support s nine p dma channels and one crc channel . each pdma channel can support a unidirectional transfer ? amba ahb master/slave interface compatible, for data transfer and register read/write ? hardware round robin priority scheme . dma channel 0 has the highest priority and channel 8 has the lowest priority ? pdma operation C peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer C support s word/half - word/byte transfer data width from/to peripheral C support s address direction: incremen t, fixed. ? cyclic redundancy check (crc) C supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 C supports p rogrammable crc seed value. C support s programmable order reverse setting for input data and crc checksum. C support s programmable 1s complement setting for input data and crc checksum. C support s cpu pio mode or dma transfer mode. C support s the follows write data length in cpu pio mode ? 8 - bit write mode (byte): 1 - ahb clock cycle operation. ? 16 - bit write mode (half - word): 2 - ahb clock cycle operation. ? 32 - bit write mode (word): 4 - ahb clock cycle operati on. C support s byte alignment transfer data length and word alignment transfer source address in crc dma mode.
nuc100/120xxxdn aug 31 , 201 5 page 70 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet timer controller (tmr) 6.8 6.8.1 overview the timer controller includes four 32 - bit timers, timer0~timer3, allow ing user to easily implement a timer control for applications. the timer can perform functions , such as frequency measurement, event counting, interval measurement, clock generation, and delay timing . the timer can generate an interrupt signal upon time - out, or provide the current value during operation. 6.8.2 features ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle and continuous counting operation modes ? time - out period = (period of timer clock input) * (8 - bit prescale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24 - bit up counter value is readable through tdr (timer data register) ? su pport s event counting function to count the event from external pin ? support s external pin capture function for interval measurement ? support s external pin capture function for reset timer counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated (tif set to 1)
nuc100/120xxxdn aug 31 , 201 5 page 71 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet pwm generator and capture timer (pwm) 6.9 6.9.1 overview the numicro ? nuc 1 00 series has 2 sets of pwm group s support ing a total of 4 sets of pwm g enerators that can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable d ead - zone generators. each pwm g enerator has one 8 - bit prescaler, one clock divid er with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm counters for pwm period control, two 16 - bit comparators for pwm duty control and one d ead - zone generator. the 4 sets of pwm g enerators prov ide eight independent pwm interrupt flags set by hardware when the corresponding pwm period down counter reaches 0 . each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perform complementary pwm paired function; the paired pwm period, duty and d ead - time are determined by pwm0 ti mer and dead - zone generator 0. similarly, the complementary pwm pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead - zone generator 2, 4 and 6, respectively. to prevent pwm driving output pin with unst eady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16 - bit down counter/ comparator at the time down co unter reaching 0 . the double buffering feature avoids glitch at pwm outputs. when the 16 - bit period down counter reaches 0 , the interrupt request is generated. if pwm - timer is set as auto - reload mode, when the down counter reaches 0 , it is reloaded with pw m counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm - timer is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches 0 . the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down - counter value matches the value of compare register. the alternate feature of the pwm - timer is digital input capture function. if capture function is enabled the pwm ou tput pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm - timer before enable capture feature. after capture feature is enabled, the capture always latched pwm - counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm - counter to capture falling latch register (cflr) when input channel has a falling transition. capture channe l 0 interrupt is programmable by setting ccr0. c rl_ie0[1] (rising latch interrupt enable) and ccr0. c fl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0. c rl_ie1[17] an d ccr0. c fl_ie1[18]. and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr2. for each group, whenever capture issues interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this moment. the maximum captured frequency that pwm can capture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, including : read piir to get interrupt source and read crl r x/cfl r x(x=0~3) to get captur e value and finally write 1 to clear piir to 0 . if interrupt latency will take time t0 to finish, the capture signal mustnt transition during this interval (t0). in this case, the maximum capture frequency will be 1/t0. for example: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns
nuc100/120xxxdn aug 31 , 201 5 page 72 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet so the maximum capture frequency will be 1/900ns = 1000 khz 6.9.2 features pwm f unction: 6.9.2.1 ? up to 2 pwm group s (pwma/pwmb) to support 8 pwm channels or 4 complementary pwm paired channels ? each pwm group has two pwm generators with e ach pwm generator support ing one 8 - bit prescaler, two clock divider, two pwm - timers, one d ead - zone generator and two pwm outputs. ? up to 16 - bit resolution ? pwm interrupt request synchronized with pwm period ? one - shot or auto - reload mode pwm ? edge - aligne d type or c enter - aligned type option capture function: 6.9.2.2 ? timing control logic shared with pwm generators ? support s 8 capture input channels shared with 8 pwm output channels ? each channel supports one rising latch register (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
nuc100/120xxxdn aug 31 , 201 5 page 73 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet watchdog timer (wdt) 6.10 6.10.1 overview the purpose of watchdog timer is to perform a system reset when system runs into an unknown state . this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/ p ower - down mode. 6.10.2 features ? 18 - bit free running up counter for watchdog t imer time - out interval . ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 104 m s ~ 2 6 . 3168 s if wdt_clk = 1 0 k hz. ? system kep t in reset state for a period of (1 / wdt_clk) * 63 ? supports selectable watchdog t imer reset delay period, it includes (1024+2) (128+2) (16+2) or (1+2) wdt_clk reset delay period . ? supports force watchdog t imer enabled after chip powered on or reset while cwdten (config0[31] watchdog enable) bit is set to 0. ? supports watchdog t imer time - out wake - up function when wdt clock source is selected to 10 khz low speed oscillator.
nuc100/120xxxdn aug 31 , 201 5 page 74 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet window watchdog timer (wwdt) 6.11 6.11.1 overview the pur pose of window watchdog timer is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 features ? 6 - bit down counter (wwdtval[5:0]) and 6 - bit compare value (wwdtcr[21:16] C wincmp value) to make the window period flexible ? selectable maximum 11 - bit wwdt clock prescale (wwdtcr[11:8] C periodsel value) to make wwdt time - out interval variable
nuc100/120xxxdn aug 31 , 201 5 page 75 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet real time clock (rtc) 6.13 6.13.1 overview the real time clock (rtc) controller provides user with the real time and calendar message. the clock source of rtc controller is from an external 32.768 khz low speed crystal which connected at pins x32i and x32o (refer to pin d escription) or from an external 32.768 khz low speed oscillator output fed at pin x32i. the rtc controller provides the real time message (hour , minute , second) in tlr (rtc time loading register ) as well as calendar message (year , month , day) in clr (rtc calendar loa ding register ) . it also offers rtc alarm function that user can preset the alarm time in tar (rtc time alarm register ) and alarm calendar in car (rtc calendar alarm register ) . the data format of rtc time and calendar message are all expressed in bcd format . the rtc controller supports periodic rtc time tick and alarm match interrupts. the periodic rtc time tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0] time tick register ). when real time and calendar message in tlr and clr are equal to alarm time and calendar setting s in tar and car, the aif (riir [0] rtc alarm interrupt flag ) is set to 1 and the rtc alarm interrupt signal is generated if the aier (rier [0] alarm interrupt enable ) is enabled. both rtc time tick and alarm match interrupt signal can cause chip to wake - up from idle or p ower - down mode if the correlate interrupt enable bit (aier or tier) is set to 1 before chip enter s idle or p ower - down mode . 6.13.2 features ? supports re al time counter in tlr (hour , minute , second) and calendar counter in clr (year , month , day) for rtc time and calendar check ? supports alarm time (hour , minute , second ) and calendar (year , month , day) settings in tar and car ? selectable 12 - hour or 24 - hour time scale in tssr register ? supports leap y ear indication in lir register ? supports day of the w eek counter in dwr register ? frequency of rtc clock source compensate by fcr register ? all time and calendar message expressed in bcd format ? support s periodic rtc t ime t ick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? support s rtc time tick and alarm match interrupt ? support s chip wake - up from idle or p ower - down mode while a rtc interrupt signal is generated
nuc100/120xxxdn aug 31 , 201 5 page 76 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet uart inte rface controller (uart) 6.14 the numicro ? nuc1 00 series provides up to three channels of universal asynchronous receiver/transmitters (uart). uart0 supports high speed uart and uart1~2 perform normal speed uart . b esides , only uart0 and uart1 support the flow control function. 6.14.1 overview the universal asynchronous receiver/transmitter (uart) performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda sir, lin master/slave mode and rs - 485 mode functions. each uart channel supports seven types of interrupts including : ? t ransmitter fifo empty interrupt (int_thre ) ? r eceiver threshold level reach ed interrupt (int_rda), ? l ine status interrupt (parity error or fram e error or break interrupt) (int_rls), ? r eceiver buffer time - out interrupt (int_tout), ? modem/wake - up status interrupt (int_modem), ? buffer error interrupt (int_buf_err) ? lin interrupt (int_lin) i nterrupts of uart0 and uart2 share the inte rrupt number 12 (vector number is 28); interrupt number 13 (vector number is 29) only supports uart1 interrupt. refer to the nested vectored interrupt controller chapter f or system interrupt map. the uart0 is built - in with a 64 - byte transmitter fifo ( tx _fifo) and a 64 - byte receiver fifo (rx_fifo) that reduces the number of interrupts presented to the cpu . the uart1~2 are equipped with 16 - byte transmitter fifo ( tx _fifo) and 16 - byte receiver fifo (rx_fifo). the cpu can read the status of the uart at any ti me during the operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as 4 error conditions (parity error, fram e error, break interrupt and buffer error) probably occur whil e receiving data. the uart includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. the baud rate equation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud) . table 6 - 6 lists the equations in the various conditions and table 6 - 7 list s the uart baud rate setting table. mode div _ x _ en div _ x _ one divider x brd baud r ate e quation 0 0 0 dont care a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 dont care a uart_clk / (a+2), a must >=3 table 6 - 6 uart baud rate equation system c lock = i nternal 2 2 . 1 184 mhz h igh s peed o scillator baud r ate mode 0 mode 1 mode 2 parameter register parameter register parameter register 921600 x x a=0,b=11 0x2b00_0000 a=22 0x3000_0016
nuc100/120xxxdn aug 31 , 201 5 page 77 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 460800 a=1 0x0000_0001 a=1,b=15 a=2,b=11 0x2f00_0001 0x2b00_0002 a=46 0x3000_002e 230400 a=4 0x0000_0004 a=4,b=15 a=6,b=11 0x2f00_0004 0x2b00_0006 a=94 0x3000_005e 115200 a=10 0x0000_000a a=10,b=15 a=14,b=11 0x2f00_000a 0x2b00_000e a=190 0x3000_00be 57600 a=22 0x0000_0016 a=22,b=15 a=30,b=11 0x2f00_0016 0x2b00_001e a=382 0x3000_017e 38400 a=34 0x0000_0022 a=62,b=8 a=46,b=11 a=34,b=15 0x2800_003e 0x2b00_002e 0x2f00_0022 a=574 0x3000_023e 19200 a=70 0x0000_0046 a=126,b=8 a=94,b=11 a=70,b=15 0x2800_007e 0x2b00_005e 0x2f00_0046 a=1150 0x3000_047e 9600 a=142 0x0000_008e a=254,b=8 a=190,b=11 a=142,b=15 0x2800_00fe 0x2b00_00be 0x2f00_008e a=2302 0x3000_08fe 4800 a=286 0x0000_011e a=510,b=8 a=382,b=11 a=286,b=15 0x2800_01fe 0x2b00_017e 0x2f00_011e a=4606 0x3000_11fe table 6 - 7 uart baud rate setting table the uart0 and uart1 controllers support the auto - flow control function that uses two low - level signals, / cts (clear - to - send) and / rts (request - to - send), to control the flow of data transfer between the chip and external devices ( e.g. modem). when auto - flow is enabled, the uart is not allowed to rece ive data until the uart asserts / rts to external device. when the number of bytes in the rx fifo equals the value of rts_tri_lev (ua_fcr [19:16]), the / rts is de - asserted. the uart sends data out when uart controller detects / cts is asserted from external device. if a valid asserted / cts is not detected the uart controller will not send data out. figure 6 - 16 uart nrts auto - flow control trigger level the uart controllers also provides serial irda (sir, serial infrared) function (user must set irda_en (ua_fun_sel [1]) to enable irda function). the sir specification defines a short - range infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. the maximum data rate supports up to 115.2 kbps (half duplex). the irda sir block contains an irda m c r [ r t s ] m c r [ r t s _ s t ] u a r t m o d e : m c r [ l e v _ r t s ] = 1 m c r [ r t s ] m c r [ r t s _ s t ] u a r t m o d e : m c r [ l e v _ r t s ] = 0
nuc100/120xxxdn aug 31 , 201 5 page 78 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet sir protocol encoder/decoder. the irda sir p rotocol encoder/decoder is half - duplex only. so it cannot transmit and receive data at the same time. the irda sir physical layer specifies a minimum 10ms transfer delay between transmission and reception , and t his delay feature must be implemented by software. the alternate function of uart controllers is lin (local interconnect network) f unction. the lin mode is selected by setting the ua_fun_sel[1:0] to 01 . in lin mode, 1 start bit and 8 data bits format with 1 stop bit are required in accordance with the lin standard. for numicro ? nuc 1 00 s eries , another alternate function of uart contr ollers is rs - 485 9 - bit mode, and direction control provided by / rts pin or can program gpio (pb.2 for uart0_n rts and pb.6 for uart1_n rts) to implement the function by software. the rs - 485 mode is selected by setting the ua_fun_sel register to select rs - 485 function. the rs - 485 transceiver control is implemented using the / rts control signal from an asynchronous serial port to enable the rs - 485 transceiver . in rs - 485 mode, many characteristics of the receiving and transmitting are same as uart. 6.14.2 features ? full duplex, asynchronous communications ? separate s receive / transmit 64/16/16 bytes (uart0/uart1/uart2) entry fifo for data payloads ? support s hardware auto flow control/flow control function (cts, rts) and programmable rts flow control trigger level (uart 0 and uart1 support) ? programmable receiver buffer trigger level ? support s programmable baud - rate generator for each channel individually ? support s cts wake - up function (uart0 and uart1 support) ? support s 7 - bit receiver buffer time - out detection function ? uart0/uart1 can through dma channels to receive/transmit data ? programmable transmitting data delay time between the last stop and the next start bit by setting ua_tor [dly] register ? support s break error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programmable serial - interface characteristics C programmable data bit length , 5 - , 6 - , 7 - , 8 - bit character C programmable parity bit, even, odd, no parity or st ick parity bit generation and detection C programmable stop bit length , 1, 1.5, or 2 stop bit generation ? irda sir function mode C support s 3 - /16 - bit duration for normal mode ? lin function mode C support s lin master/slave mode C support s programmable break generatio n function for transmitter C support s break detect function for receiver ? rs - 485 function mode.
nuc100/120xxxdn aug 31 , 201 5 page 79 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet C support s rs - 485 9 - bit mode C support s hardware or software direct enable control provided by rts pin
nuc100/120xxxdn aug 31 , 201 5 page 80 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet smart card host interface (sc) 6.15 6.15.1 overview the smart card interface controller (sc controller) is based on iso/iec 7816 - 3 standard and fully compliant with pc/sc specifications. it also provides status of card insertion/removal. 6.15.2 features ? iso7816 - 3 t=0, t=1 compliant ? emv2000 compliant ? support s up to t hree iso7816 - 3 ports ? separate s receive / transmit 4 byte entry buffer for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? one 24 - bit and two 8 - bit time - out counter s for answer to request (atr) and waiting times processing ? support s auto inverse convention function ? support s transmitter and receiver error retry and error retry number limitation function ? support s hardware activation sequence process ? support s hardware war m reset sequence process ? support s hardware deactivation sequence process ? support s hardware auto deactivation sequence when detect ing the card removal
nuc100/120xxxdn aug 31 , 201 5 page 81 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet ps / 2 device controller (ps2d) 6.16 6.16.1 overview the ps/2 device controller provides a basic timing control for ps/2 communication. all communication between the device and the host is managed through the clk and data pins. unlike ps/2 keyboard or mouse device controller, the receive/transmit code need s to be translated as meaningful code by firmware. the device con troller generates the clk signal after receiving a r equest to s end state , but host has ultimate control over communication. data of data line sent from the host to the device is read on the rising edge and sent from the device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. s oftware can select 1 to 16 bytes for a continuous transmission. 6.16.2 features ? host communication inhibit and r equest to s end state detection ? reception frame error detection ? programmable 1 to 16 bytes transmit buffer to reduce cpu intervention ? double buffer for data reception ? s oftware overrid e bus
nuc100/120xxxdn aug 31 , 201 5 page 82 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet i 2 c serial interface controller (i 2 c) 6.17 6.17.1 overview i 2 c is a two - wire, bidirectional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a s lave . data bits transfer on the scl and sda lines are synchronously on a byte - by - byte basis. each data byte is 8 - bit long. there is one scl clock pulse for each data bit with the msb being transmitted first , and a n acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a comm and (start or stop). please refer to figure 6 - 17 for more detail ed i 2 c bus timing. figure 6 - 17 i 2 c bus timing the devices on - chip i 2 c logic provides a serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c hardware interfaces to the i 2 c bus via two pins: sda and scl. p ull - up resistor is needed for i 2 c operation as the sda and scl are open drain pins. when i/o pins are used as i 2 c port s , user must set the pins function to i 2 c in advance. t b u f s t o p s d a s c l s t a r t t h d ; s t a t l o w t h d ; d a t t h i g h t f t s u ; d a t r e p e a t e d s t a r t t s u ; s t a t s u ; s t o s t o p t r
nuc100/120xxxdn aug 31 , 201 5 page 83 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 6.17.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus include : ? master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow ing devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? a b uilt - in 14 - bit time - out cou nter request ing the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows ? external pull - up resistors needed for high output ? programmable clocks allow ing for versatile rate control ? supports 7 - bit addressing mode ? s upport s multiple address recognition ( f our slave address es with mask option)
nuc100/120xxxdn aug 31 , 201 5 page 84 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet serial peripheral interface (spi) 6.18 6.18.1 overview the serial peripheral interface ( spi ) is a synchronous serial data communication protocol that operates in full duplex mode. devices communicate in m aster/ slave mode with the 4 - wire bi - direction interface. the numicro ? nuc 1 00 series contains up to four sets of spi controller s perform ing a serial - to - parallel conversion on data received from a periph eral device , and a parallel - to - serial conversion on data transmitted to a peripheral device . each set of spi controller can be configured as a master or a slave device . th e spi controller supports the variable serial clock function for special application s and 2 - bit t ransfer mode to connect 2 off - chip slave devices at the same time. this controller also supports the pdma function to access the data buffer and also support s d ual i / o t ransfer mode. 6.18.2 features ? up to four sets of spi controller s ? support s m aster o r slave mode operation ? support s 2 - bit t ransfer mode ? support s d ual i / o t ransfer mode ? configurable bit length of a transfer word from 8 to 32 - bit ? provide s separate 8 - layer depth transmit and receive fifo buffers ? support s msb first or lsb first transfer sequence ? two slave select li nes in master mode ? support s the byte reorder function ? support s b yte or w ord s uspend mode ? variable output serial clock frequency in master mode ? support s pdma transfer ? support s 3 - wire, no slave select signal, bi - direction interface
nuc100/120xxxdn aug 31 , 201 5 page 85 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet i 2 s controller (i 2 s) 6.19 6.19.1 overview the i 2 s controller consists of i 2 s protocol to interface with external audio codec. two 8 - word deep fifo for read path and write path respectively and is capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes. p dma controller handle s the data movement between fifo and memory. 6.19.2 features ? o perate d as either m aster or s lave ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes ? supports mono a nd stereo audio data ? supports i 2 s and msb justified data format ? provides t wo 8 - word fifo data buffers, one fo r transmit ting and the other for receiv ing ? generates interrupt requests when buffer levels cross a program mable boundary ? two p dma requests, one f or transmit ting and the other for receiv ing
nuc100/120xxxdn aug 31 , 201 5 page 86 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet usb device controller (usb) 6.20 6.20.1 overvi ew there is one set of usb 2.0 full - speed device controller and transceiver in this device . it is compliant with usb 2.0 full - speed device specification and support s control/bulk/interrupt/ isochronous transfer types. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is nec essary to write data to sram or read data from sram through the apb interface or sie. user needs to set the effective starting address of sram for each endpoint buffer through buffer segmentation register ( usb_ bufsegx). there are 6 endpoints in this cont roller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of endpoint control is also used to manage the data sequential syn chronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the wake - up function, device plug - in or plug - out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any e vent will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge what kind of event occurring in t his endpoint . a software - disable function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables drv se0 bit (usb_drvse0), the usb controller will force the output of usb_dp and usb_ dm to level low and its function is disabled . after disable the drv se0 bit , host will enumerate the usb device again. please refer to universal serial bus specification revision 1.1 6.20.2 features this universal serial bus (usb) performs a serial interface with a single connector type for attaching all usb peripherals to the host system. following is the feature list of this usb. ? compliant with usb 2.0 full - speed specification ? provide s 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) ? support s control/bulk/interrupt/isochronous transfer type ? support s suspend function when no bus activity existing for 3 ms ? provide s 6 endpoints for configurable control/bulk/interrupt/isochronous transfer types and maximum 512 bytes buffer size ? provide s remote wake - up capability
nuc100/120xxxdn aug 31 , 201 5 page 87 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet analog - to - digital converter (adc) 6.21 6.21.1 overview the numicro ? nuc1 00 s eries contain s one 12 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels. the a/d converter supports three operation modes: single, single - cycle scan and continuous scan mode. the a/d converter can be started by software , pwm c enter - aligned trigger and external stadc pin. 6.21.2 features ? analog input voltage range: 0~v ref ? 12 - bit resolution and 10 - bit accuracy is guaranteed ? up to 8 single - end analog input channels or 4 differential analog input channels ? up to 7 6 0 k sps conversion rate as adc clock frequency is 16 mhz ( chip working at 5v ) ? three operating modes C single mode: a/d conversion is performed one time on a specified channel C single - cycle scan mode: a/d conversion is performed one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel C continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion ? an a/d c onversion can be started by : C w rit ing 1 to adst bit through software C pwm c enter - aligned trigger C external pin stadc ? conversion results are held in data registers for each channel with valid and overrun indicators ? conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting ? channel 7 supports 3 input sources: external analog voltage, internal band - gap voltage, an d internal temperature sensor output
nuc100/120xxxdn aug 31 , 201 5 page 88 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet analog comparator ( a cmp) 6.22 6.22.1 overview the numicro ? nuc1 00 s eries contains two comparators which can be used in a number of different configurations. the comparator output is logic 1 when positive input voltage is greater than negative input voltage ; otherwise the output is logic 0 . each comparator can be configured to cause an interrupt when the comparator output value changes. 6.22.2 features ? analog input voltage range: 0~ v dda ? supports hysteresis function ? supports optional internal reference voltage input at negative end for each comparator
nuc100/120xxxdn aug 31 , 201 5 page 89 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 7 application circuit a v s s a v d d a v c c d v c c v s s v d d 4 ~ 2 4 m h z c r y s t a l 0 . 1 u f f b f b 2 0 p 2 0 p d v c c 1 0 u f / 2 5 v 1 0 k p o w e r c r y s t a l r e s e t c i r c u i t / r e s e t x t 1 _ o u t l d o n u c 1 x x s e r i e s v d d v s s / r e s e t i c e _ c l k i c e _ d a t s w d i n t e r f a c e 1 u f v d d v s s i 2 c d e v i c e c l k d i o i 2 c 0 s d a i 2 c 0 s c l 4 . 7 k v d d v s s s p i d e v i c e c s c l k m i s o s p i s s 0 0 m o s i s p i c l k 0 m i s o 0 0 m o s i 0 0 l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t x t 1 _ i n 0 . 1 u f d v c c 4 . 7 k d v c c d v c c n o t e : f o r t h e s p i d e v i c e , t h e c h i p s u p p l y v o l t a g e m u s t b e e q u a l t o s p i d e v i c e w o r k i n g v o l t a g e . f o r e x a m p l e , w h e n t h e s p i f l a s h w o r k i n g v o l t a g e i s 3 . 3 v , t h e n u c 1 x x c h i p s u p p l y v o l t a g e m u s t a l s o b e 3 . 3 v . u a r t [ 1 ] r x d t x d s m a r t c a r d v c c u s b p o r t d + d - 3 3 3 3 v b u s v s s
nuc100/120xxxdn aug 31 , 201 5 page 90 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 8 electrical character istics absolute maximum ratings 8.1 symbol parameter min. max unit dc power supply v dd ? v ss - 0.3 +7.0 v input voltage v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta - 40 +85 ? c storage temperature tst - 55 +150 ? c maximum current into v dd - 120 ma maximum current out of v ss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
nuc100/120xxxdn aug 31 , 201 5 page 91 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet dc electrical characteristics 8.2 (v dd - v ss = 5.5 v, t a = 25 ? c, f osc = 50 mhz unless otherwise specified.) parameter sym. specification test conditions min. typ. max. unit operation v oltage v dd 2.5 5.5 v v dd = 2.5v ~ 5.5v up to 50 mhz power ground v ss av ss - 0.3 v ldo output voltage v ldo 1.62 1.8 1.98 v v dd > 2. 5 v analog operating voltage av dd v dd v when system used analog function, please refer to chapter 8.4 for corresponding analog operating voltage operating current normal run mode at 50 mhz i dd1 34 ma v dd xtal pll all ip 5.5v 12 mhz v v i dd2 15 ma 5.5v 12 mhz v x i dd3 32 ma 3.3v 12 mhz v v i dd4 14 ma 3.3v 12 mhz v x operating current normal run mode at 12 mhz i dd5 8.5 ma v dd xtal pll all ip 5.5v 12 mhz x v i dd6 3.6 ma 5.5v 12 mhz x x i dd7 7.5 ma 3.3v 12 mhz x v i dd8 2.6 ma 3.3v 12 mhz x x operating current normal run mode at 4 mhz i dd9 3.6 ma v dd xtal pll all ip 5.5v 4 mhz x v i dd10 2 ma 5.5v 4 mhz x x i dd11 2.8 ma 3.3v 4 mhz x v i dd12 1.2 ma 3.3v 4 mhz x x operating current normal run mode at 32.768 khz i dd13 141 ? a v dd xtal pll all ip 5.5v 32.768 khz x v i dd14 129 ? a 5.5v 32.768 khz x x i dd15 138 ? a 3.3v 32.768 khz x v
nuc100/120xxxdn aug 31 , 201 5 page 92 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet parameter sym. specification test conditions min. typ. max. unit i dd16 125 ? a 3.3v 32.768 khz x x operating current normal run mode at 10 khz i dd17 125 ? a v dd lirc pll all ip 5.5v 10 khz x v i dd18 120 ? a 5.5v 10 khz x x i dd19 125 ? a 3.3v 10 khz x v i dd20 120 ? a 3.3v 10 khz x x operating current idle mode at 50 mhz i idle1 28 ma v dd xtal pll all ip 5.5v 12 mhz v v i idle2 10 ma 5.5v 12 mhz v x i idle3 27 ma 3.3v 12 mhz v v i idle4 9 ma 3.3v 12 mhz v x operating current idle mode at 12 mhz i idle5 7.5 ma v dd xtal pll all ip 5.5v 12 mhz x v i idle6 2.4 ma 5.5v 12 mhz x x i idle7 6.5 ma 3.3v 12 mhz x v i idle8 1.5 ma 3.3v 12 mhz x x operating current idle mode at 4 mhz i idle9 3.3 ma v dd xtal pll all ip 5.5v 4 mhz x v i idle10 1.7 ma 5.5v 4 mhz x x i idle11 2.4 ma 3.3v 4 mhz x v i idle12 0.8 ma 3.3v 4 mhz x x operating current idle mode at 32.768 k hz i idle 13 133 ? a v dd xtal pll all ip 5.5v 32.768 khz x v i idle1 4 120 ? a 5.5v 32.768 khz x x i idle1 5 133 ? a 3.3v 32.768 khz x v i idle1 6 120 ? a 3.3v 32.768 khz x x operating current i idle 13 122 ? a v dd lirc pll all ip
nuc100/120xxxdn aug 31 , 201 5 page 93 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet parameter sym. specification test conditions min. typ. max. unit idle mode at 10 k hz 5.5v 10 khz x v i idle1 4 118 ? a 5.5v 10 khz x x i idle1 5 122 ? a 3.3v 10 khz x v i idle1 6 118 ? a 3.3v 10 khz x x standby current power - down mode (deep sleep mode) i pwd1 15 ? a v dd rtc bod function 5.5v x x i pwd 2 15 ? a 5.5v x x i pwd 3 17 ? a 3.3v x x i pwd 4 17 ? a 3.3v x x input current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i in1 - 50 - 60 ? a v dd = 5.5v, v in = 0v or v in =v dd input current at /reset [1] i in2 - 55 - 45 - 30 ? a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe , pf i lk - 2 - + 2 ? a v dd = 5.5v, 0 nuc100/120xxxdn aug 31 , 201 5 page 94 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet parameter sym. specification test conditions min. typ. max. unit input low voltage x32i [*2] v il 4 0 - 0.4 v input high voltage x32i [*2] v ih 4 1.2 1.8 v negative going threshold (schmitt input), /reset v ils - 0.5 - 0. 2 v dd - 0. 2 v positive going threshold (schmitt input), /reset v ihs 0.7v dd - v dd +0.5 v source current pa, pb, pc, pd, pe , pf (quasi - b idirectional mode) i sr11 - 30 0 - 37 0 - 45 0 ? a v dd = 4.5v, v s = 2.4v i sr12 - 50 - 7 0 - 9 0 ? a v dd = 2.7v, v s = 2.2v i sr12 - 40 - 60 - 80 ? a v dd = 2.5v, v s = 2.0v source current pa, pb, pc, pd, pe , pf (push - pull mode) i sr21 - 24 - 28 - 32 ma v dd = 4.5v, v s = 2.4v i sr22 - 4 - 6 - 8 ma v dd = 2.7v, v s = 2.2v i sr22 - 3 - 5 - 7 ma v dd = 2.5v, v s = 2.0v sink current pa, pb, pc, pd, pe , pf (quasi - bidirectional and push - pull mode) i sk1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 7 10 13 ma v dd = 2.7v, v s = 0.45v i sk1 6 9 12 ma v dd = 2.5v, v s = 0.45v brown - out v oltage with bo d _vl [1:0] = 00b v bo2. 2 2. 1 2. 2 2. 3 v brown - out v oltage with bo d _vl [1:0] = 01b v bo2. 7 2.6 2.7 2.8 v brown - out voltage with bo d _vl [1:0] = 10b v bo3. 7 3. 5 3. 7 3. 9 v brown - out v oltage with bo d _vl [1:0] = 11b v bo4. 4 4. 2 4. 4 4. 6 v hysteresis range of bod voltage v b h 30 - 1 5 0 mv v dd = 2.5v~5.5v band - gap voltage v bg 1. 175 1.2 0 1.2 25 v v dd = 2.5v - 5.5v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd , pe and p f can source a transition current when they are being ex ternally driven from 1 to 0. in the condition of v dd = 5.5 v, t he transition current reaches its maximum val ue when v in approximates to 2 v.
nuc100/120xxxdn aug 31 , 201 5 page 95 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet ac electrical characteristics 8.3 8.3.1 external 4~24 mhz high speed oscillator note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time 1 0 - - ns t clcx clock low time 1 0 - - ns t clch clock rise time 2 - 1 5 ns t chcl clock fall time 2 - 1 5 ns 8.3.2 external 4~24 mhz high speed crystal parameter condition min. typ.. max. unit operation voltage v dd - 2. 5 - 5.5 v temperature - - 40 - 85 operating c urrent 12 mhz at v dd = 5v - 1 - ma c lock f requency external crystal 4 24 mhz typical crystal application circuits 8.3.2.1 crystal c1 c2 r 4 mhz ~ 24 mhz 10~20pf 10~20pf without t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d
nuc100/120xxxdn aug 31 , 201 5 page 96 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet figure 8 - 1 typical crystal application circuit 8.3.3 external 32.768 khz low speed crystal oscillator parameter condition min. typ. max. unit operation voltage v dd - 2. 5 - 5.5 v operation temperature - - 40 - 85 operation current 32.768khz at v dd =5v 1.5 ? a c lock f requency external crystal - 32 .768 - khz 8.3.4 internal 22.1184 mhz high speed oscillator parameter condition min. typ. max. unit operation voltage v dd - 2.5 - 5.5 v center frequency - - 22.1184 - mhz calibrated internal oscillator frequency +25 ; v dd =5 v - 1 - +1 % - 40 ~+85 ; v dd =2.5 v~5.5 v - 3 - +3 % operation current v dd =5 v - 500 - ua 8.3.5 internal 10 khz low speed oscillator parameter condition min. typ. max. unit operation voltage v dd - 2.5 - 5.5 v center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd =5 v - 30 - +30 % x t 1 _ i n x t 1 _ o u t c 1 r c 2
nuc100/120xxxdn aug 31 , 201 5 page 97 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet - 40 ~+85 ; v dd =2.5 v~5.5 v - 50 - +50 % analog characteristics 8.4 8.4.1 12 - bit saradc specification symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinearity error - - 1~2 - 1~4 lsb inl integral nonlinearity error - 2 4 lsb eo offset error - 1 10 lsb eg gain error (transfer gain) - 1 1.005 - - monotonic guaranteed f adc adc clock frequency (av dd = 5v/3v) - - 16/8 mhz f s sample rate - - 7 60 k sps v dd a supply voltage 3 - 5.5 v i dd supply current (avg.) - 0.5 - ma i dda - 1.5 - ma v ref reference voltage 3 v dd a v i ref reference current (avg.) - 1 - ma v in input voltage 0 - v ref v 8.4.2 ldo and power m anagement specification parameter min. typ. max. unit note input voltage v dd 2. 5 5.5 v v dd input voltage output voltage 1.62 1.8 1.98 v v dd > 2.5 v operating temperature - 40 25 85 c bp - 1 - ? f r esr = 1 ? note: 1. it is recommended that a 10 uf or higher capacitor and a 100 nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. to ensur e power stability, a 1 ? f or higher capacitor must be connected between ldo _cap pin and the closest v ss pin of the device.
nuc100/120xxxdn aug 31 , 201 5 page 98 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 8.4.3 low voltage reset specification paramet er condition min. typ. max. unit operation v oltage - 0 - 5.5 v quiescent c urrent v dd =5.5 v - 1 5 ? a operation t emperature - - 40 25 85 threshold v oltage temperature=25 1.7 2.0 2.3 v temperature= - 40 - 2.4 - v temperature=85 - 1.6 - v hysteresis - 0 0 0 v 8.4.4 brown - out detector specification parameter condition min. typ. max. unit operation v oltage - 0 - 5.5 v temperature - - 40 25 85 quiescent c urrent av dd =5.5 v - - 125 a brown - out v oltage bo d _vl [1:0]=11 4. 2 4. 4 4.6 v bo d _vl [1:0]=10 3. 5 3. 7 3.9 v bo d _vl [1:0]=01 2.6 2.7 2.8 v bo d _vl [1:0]=00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 mv 8.4.5 power - o n reset specification parameter condition min. typ. max. unit operation temperature - - 40 25 85 reset v oltage v+ - 2 - v quiescent c urrent vin > reset voltage - 1 - na
nuc100/120xxxdn aug 31 , 201 5 page 99 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 8.4.6 temperature sensor specification parameter conditions min. typ. max. unit operation v oltage [1] 2.5 - 5.5 v operation t emperature - 40 - 8 5 current c onsumption 6.4 - 10.5 a gain - 1.76 mv/ offset voltage temp=0 720 mv note: internal operation voltage comes from internal ldo. 8.4.7 comparator specification parameter condition min. typ. max. unit operation voltage a v dd - 2. 5 5.5 v operation temperature - - 40 25 85 operation c urrent v dd =3 .0 v - 20 40 a input o ffset v oltage - - 5 15 mv output s wing - 0.1 - v dd - 0.1 v input c ommon m ode r ange - 0.1 - v dd - 1.2 v dc g ain - - 70 - db propagation d elay vcm=1.2 v and vdiff=0.1 v - 200 - ns comparison v oltage 20 mv at vcm=1 v 50 mv at vcm=0.1 v 50 mv at vcm=v dd - 1.2 10 mv for non - hysteresis 10 20 - mv hysteresis vcm=0.4 v ~ v dd - 1.2 v - 10 - mv wake - up t ime cinp=1.3 v cinn=1.2 v - - 2 s
nuc100/120xxxdn aug 31 , 201 5 page 100 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 8.4.8 usb phy specification usb dc electrical characteristics 8.4.8.1 symbol parameter conditions min. typ. max. unit v ih input h igh (driven) 2.0 v v il input l ow 0.8 v v di differential i nput s ensitivity |padp - padm| 0.2 v v cm differential c ommon - mode r ange includes v di range 0.8 2.5 v v se single - ended r eceiver t hreshold 0.8 2.0 v receiver h ysteresis 200 mv v ol output l ow (driven) 0 0.3 v v oh output h igh (driven) 2.8 3.6 v v crs output s ignal c ross v oltage 1.3 2.0 v r pu pull - up r esistor 1.425 1.575 k v trm termination voltage for u pstream p ort p ull - up (rpu) 3.0 3.6 v z drv driver o utput r esistance steady state drive* 10 c in transceiver c apacitance pin to gnd 20 pf *driver output resistance doesnt include series resistor resistance. usb full - speed driver electrical characteristics 8.4.8.2 symbol parameter conditions min. typ. max. unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and f all t ime m atching t frff =t fr /t ff 90 111.11 % usb power dissipation 8.4.8.3 symbol parameter conditions min. typ. max. unit i v bus v bus current (steady state) standby 50 a
nuc100/120xxxdn aug 31 , 201 5 page 101 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet usb ldo specification 8.4.8.4 symbol parameter conditions min. typ. max. unit v bus vbus pin input voltage 4.0 5.0 5.5 v v dd33 ldo output voltage 3.0 3.3 3.6 v c bp external bypass capacitor 1.0 - uf
nuc100/120xxxdn aug 31 , 201 5 page 102 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet flash dc electrical characteristics 8.5 symbol parameter conditions min. typ. max. unit v dd supply v oltage 1.62 1.8 1.98 v [ 1 ] t ret data retention at 85 10 year t erase page e rase t ime 2 ms t mer mass e rase t ime 10 ms t prog program t ime 20 s i dd 1 read c urrent - 0.15 0.5 m a /mh z i dd 2 program/erase c urrent 7 ma i pd power d own c urrent - 1 20 a 1. v dd is source from chip ldo output voltage. 2. this table is guaranteed by design, not test in production.
nuc100/120xxxdn aug 31 , 201 5 page 103 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 9 package dimens i ons 100 - pin lqfp (14x14x1. 4 mm footprint 2.0 mm) 9.1 controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 ? 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 ? 25 26 50 51 7 5 7 6
nuc100/120xxxdn aug 31 , 201 5 page 104 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 64 - pin lqfp ( 10 x 10 x1 . 4 mm footprint 2.0 mm) 9.2 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5
nuc100/120xxxdn aug 31 , 201 5 page 105 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 48 - pin lqfp (7x7x1. 4 mm footprint 2.0 mm) 9.3 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
nuc100/120xxxdn aug 31 , 201 5 page 106 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet 10 revision h istory date rev ision description 201 4 .05.1 3 1.00 1. preliminary version . 2015.0 8 . 31 1.0 1 1. reorganize d the ch a pter sequence . 2. added a note in all clock source block diagrams of all peripheral sections that before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. 3. revised package size of 64 - pin lqfp ( 10 x 10 x1 . 4 mm footprint 2.0 mm) in section 9.2 .
nuc100/120xxxdn aug 31 , 201 5 page 107 of 107 rev 1.01 nuc 1 00/ 1 2 0xxxdn datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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